2010
DOI: 10.1007/s11265-010-0458-9
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Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Abstract: A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSEBitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSEBitSlice technique has been applied to the design and implementation of 12×12 and 42×42 bit real multipliers, a complex multiplier, a 6-t… Show more

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Cited by 3 publications
(1 citation statement)
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“…The techniques of common subexpression elimination (CSE) [ 8 , 9 ] are closed to our work. In [ 10 ], a type system for CSE of the while language is introduced.…”
Section: Related Workmentioning
confidence: 99%
“…The techniques of common subexpression elimination (CSE) [ 8 , 9 ] are closed to our work. In [ 10 ], a type system for CSE of the while language is introduced.…”
Section: Related Workmentioning
confidence: 99%