Low-cost FFT processor for DVB-T2 applications

Lin, Shin-Yo; Wey, Chin‐Long; Shieh, Ming-Der

doi:10.1109/tce.2010.5681074

Cited by 14 publications

(10 citation statements)

References 18 publications

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“…It completes a 128K-points FFT in 676.5 µs and a 1M points FFT in 14.8 ms. Table I presents the hardware comparison of this work with 2 different FFT realizations: Chen's low memory access length adaptive FFT architecture for all integral powers of 2 [5]; And a design for long length, Lin's FFT processor, which supports 32K points series [6].…”

Section: Resultsmentioning

confidence: 99%

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An ultra-long FFT architecture implemented in a reconfigurable application specified processor

Feng

Wang

et al. 2016

IEICE Electron. Express

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This paper presents an efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit. The proposed FFT architecture reduces the computation cost by taking the advantage of the radix-8 FFT algorithm while remaining compatible with sequences whose data length is an integral power of 2. Further optimizations for reconfigurable application specified processor are developed. First, we propose a separated radix-2/4/8 butterfly unit which is more flexible than an entire radix-2/4/8 butterfly unit; second, for the sequences longer than 256K points, an efficient 2-epoch FFT solution is realized. This FFT architecture is implemented in a reconfigurable application specified processor. The computation time of our architecture is 676 us and 14.8 ms for 128K and 1M points FFTs respectively.

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Section: Resultsmentioning

confidence: 99%

“…Common VLSI implementation of FFT architectures can be classified into three categories: memory-based architectures [3,4,5,6], cache-based architectures [7,8,9] and pipelined architectures [10,11,12,13]. Memory-based architectures generally consist of processing units and memory blocks.…”

Section: Introductionmentioning

confidence: 99%

An ultra-long FFT architecture implemented in a reconfigurable application specified processor

Feng

Wang

et al. 2016

IEICE Electron. Express

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“…Furthermore, Table 6 illustrates the performance comparison of this work with five recent state-of-the-art FFT chip designs [18,21,24,26], and [17]. The designs [24] and Table 6 Performance comparison with modern long-length FFT designs Design Lin et al [24] Lee and Park [21] Hung et al [18] Lin et al [26] Huang and Chen [17] T [21] are respectively the representatives of the cached-memory and the pipeline architecture.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

“…The designs [24] and Table 6 Performance comparison with modern long-length FFT designs Design Lin et al [24] Lee and Park [21] Hung et al [18] Lin et al [26] Huang and Chen [17] T [21] are respectively the representatives of the cached-memory and the pipeline architecture. The cached-memory architecture offers a major advantage of higher flexibility.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

“…The design [18] presents a variable-length FFT processor that can compute 1k/2k/4k/8k points, based on the cached-memory architecture. Furthermore, both the designs [26] and [17] adopt a rather advanced fabrication technology. The core area of [17] is obviously smaller than other designs because it deals with FFT operations with a rather shorter length, i.e., 512-point.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

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A Low-Memory-Access Length-Adaptive Architecture for 2 $$^n$$ n -Point FFT

Chen

2014

Circuits Syst Signal Process

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Fast Fourier transformation (FFT) is widely used in modern wireless communication and digital signal processing. Because memory access is a major cause of power dissipated by the long-length FFT architecture, this paper explores the design space expanded by FFT size and radix number in detail and presents a novel lowmemory-access length-adaptive architecture for computing any long-length 2 n -point FFT. The proposed hardware solution possesses the following three attractive features to reflect its novelty as compared to the existing designs. First, the authors identified that memory consumes major energy dissipation of a FFT processor and proposed to reduce memory access through decreasing the number of FFT butterfly stages. The second one is that we adopt the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware for computing variable-length FFT without sacrificing the hardware utilization as contrary to the feed-forward architecture. Finally, a 16-bank memory organization is proposed to achieve conflict-free FFT operations for various radixes. Such low-memory-access length-adaptive architecture can reduce almost 70 % memory access or 30 % power consumption for FFT computation. After being implemented through 1P6M TSMC 0.18-µm CMOS technology, this work costs a core area of only 4.49 mm 2 and meets the FFT real-time performance requirements of DVB-T2 systems when operated at 20 MHz frequency. The proposed design consumes only 1.44 nJ of energy per sample for computing FFTs. Through adopting the proposed low-memory-access algorithm, flexible length-adaptive architecture, and efficient 16-bank memory organization, 56 % power dissipation of the whole FFT chip can be saved.

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