Low Current Constant-gm Technique for Rail-to-Rail Operational Amplifiers

Veselu, Adrian; Stanescu, C.; Brezeanu, Gheorghe

doi:10.1109/cas50358.2020.9267977

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…In, [9], the simulation of the standard constant Gm technique has been demonstrated, revealing the need for high current and reliance on the square law model of transistors. The technique used in, [9], is modified in, [10], in which the current consumption is reduced by sacrificing the circuit speed. Nevertheless, both the architectures are still bound by the square law model assumption.…”

Section: Introductionmentioning

confidence: 99%

Design and Comparison of Constant Transconductance Architectures

H. L.,

N.,

A. S.

et al. 2024

Wseas Transactions on Electronics

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Constant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.

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Section: Introductionmentioning

confidence: 99%

Design and Comparison of Constant Transconductance Architectures

H. L.,

N.,

A. S.

et al. 2024

Wseas Transactions on Electronics

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A novel constant-g<sub>m</sub> rail-to-rail input stage for operational amplifiers

Chen

Wang

et al. 2023

IEICE Electron. Express

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A novel constant-gm rail-to-rail input stage for CMOS operational amplifier is presented in this paper. The input stage mainly consists of a PMOS transistors differential pair and a NMOS transistors differential pair placed in parallel as a rail-to-rail differential input stage and the tail currents of the two differential pairs are controlled by a PMOS and a NMOS common-mode voltage sensor respectively. The gm of the input stage of the operational amplifier could be a constant value within the input common-mode voltage. The simulation result shows that when the power supply voltage is 1.8V and 3.3V respectively, the gm variation in the entire input range (0~1.8V or 0~3.3V) is within ± 1.38% and ± 3.38%. The power dissipation is 36.9μW and 51.74μW. SMIC 55nm CMOS process and Cadence SPECTRE simulator are used to layout and simulate this work.

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Temperature and Power Supply Compensated CMOS Clock Circuit Based on Ring Oscillator

et al. 2023

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Improved performance operational amplifier demand has continuously increased. IC designers use the charge pump technique as an advanced solution to implement the amplifier’s rail−to−rail input stage, but the need for a large load capacitor is a serious downside. To reduce this passive component value, high−frequency clock circuits with a 50% duty cycle should be implemented. This paper focuses on designing such a circuit that is further compensated with temperature and power supply, maintaining these performances even when process variations occur, starting from a ring oscillator as the architecture core. A pre−layout 50 MHz center frequency at 25 °C with a 1.6 temperature percentage error was achieved. Post−layout simulations to account for parasitic effects were also performed, with a 48.9 MHz center frequency reached. Distinct methods that control the frequency variation were discussed and established. Performance comparison of the designed PLL with previously reported clock circuits in the CMOS process was concluded, with superior results such as power consumption, die area, and temperature range accomplished.

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Low Current Constant-gm Technique for Rail-to-Rail Operational Amplifiers

Cited by 3 publications

References 2 publications

Design and Comparison of Constant Transconductance Architectures

Design and Comparison of Constant Transconductance Architectures

A novel constant-g<sub>m</sub> rail-to-rail input stage for operational amplifiers

Temperature and Power Supply Compensated CMOS Clock Circuit Based on Ring Oscillator

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