Low Delay Based Full Adder/Subtractor by MIG and COG Reversible Logic Gate

Chacko, Jacob B.; Whig, Pawan

doi:10.1109/cicn.2016.120

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…To test the circuit of SAM, a 4-bit multiplier design and an 8-bit BILBO were used. YAG gate design [26] is used for generating sum and product terms simultaneously. Input signal always in SCAN Mode If the BILBO uses LFSR mode, it generates the no of patterns required for the multiplier and the multiplier takes the inputs and intakes the output to the BILBO, which performs the operations to generate the signature like MISR Mode.…”

Section: System Design and Testing Methodsmentioning

confidence: 99%

Design and testing of systolic array multiplier using fault injecting schemes

Jahagirdar

Rao

2022

Comput. Sci. Inf. Technol.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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Section: System Design and Testing Methodsmentioning

confidence: 99%

Design and testing of systolic array multiplier using fault injecting schemes

Jahagirdar

Rao

2022

Comput. Sci. Inf. Technol.

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“…Because we can have a better energy performance while the delay is not significantly increased as a static logic circuit [5][6]. This is an important characteristic to consider for its use in reversible neural signal processing arithmetic and logic units (ALUs) [7]. Where "delay" refers to the propagation delay on the critical path, because the delay of other paths is less important, and "energy" refers to the total energy obtained from the VDD under a given input probability distribution [8].…”

Section: General Ideamentioning

confidence: 99%

Optimized design of a 4-bits absolute-value detector based on linear programming

Wang

2024

ACE

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Nowadays, neural signal acquisition systems are constantly developing, and spike classification algorithms have been widely studied and concerned. This paper designed a practical spike detection circuit, named as the absolute value detector. Project is committed to adopting only simple gate circuits, by using Morgans theorem to optimize the circuit structure, so that we can ensure that the detector has the following several advantages, simple and beautiful, easy to understand, powerful performance. In addition, this paper also considered the optimization of performance including latency and energy consumption. The increase of Vdd will increase the energy consumption and reduce the delay, while the increase of size will reduce the energy consumption and increase the delay. Using MATLAB software for linear programming, Under the condition of a 1.5-fold increase in the delay, and then adjusting Vdd and size, energy consumption was down by 78 percent.

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