Low Electrical Resistance Silicon Through Vias: Technology and Characterization

Henry, David D.; Belhachemi, D.; Souriau, Jean-Charles; Brunet-Manquat, C.; Puget, C.; Ponthenier, G.; Vallejo, J.L.; Lecouvey, Christophe; Sillon, N.

doi:10.1109/ectc.2006.1645834

Cited by 22 publications

(11 citation statements)

References 5 publications

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“…In addition, traditional objectives, such as wire length and area, are insufficient for 3-D circuits, particularly [28], [47] and (b) 3-D SOI processes [9].…”

Section: Complexity Of 3-d Physical Design Processmentioning

confidence: 99%

“…The number of package pins also limits the clock signal and power supply networks. Additional primary challenges in 3-D circuits include the development of methodologies at the front end of the design process [21], [22], multiplane functional testing [23], thermal management techniques [68], and maturing manufacturing technologies [24]- [28].…”

Section: Introductionmentioning

confidence: 99%

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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“…In addition, traditional objectives, such as wire length and area, are insufficient for 3-D circuits, particularly [28], [47] and (b) 3-D SOI processes [9].…”

Section: Complexity Of 3-d Physical Design Processmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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“…The most important steps of the 3-D design process and related design methodologies are discussed in the remainder of this chapter. [14], [22] and (b) 3-D SOI processes [21]. …”

Section: Vertical Interconnectsmentioning

confidence: 99%

“…This heterogeneity, however, greatly complicates the interconnect design process within a multi-plane system, as potential design methodologies need to manage the diverse interconnect impedance characteristics and process variations caused by the different fabrication processes and technologies employed in the multiple physical planes [9]. Additional primary challenges in 3-D circuits include the development of methodologies at the front end of the design process [10], [11], multi-plane functional testing [12], thermal management techniques [13], and maturing manufacturing technologies [14].…”

Section: Introductionmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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“…An insulating layer of SiO 2 on the via wall can be fabricated by CVD (Chemical Vapor Deposition) or by oxidation methods. [4][5][6][7][8] Ti, which enhances the adhesion between the insulation and seed layer, has been widely adopted as an adhesion layer. 4,5,9) Cu is frequently used as a seed layer due to its low cost and lower electrical resistivity.…”

Section: Introductionmentioning

confidence: 99%

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

et al. 2010

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A new bumping process on a Si die by electroplating without a photo-resist-mold (PRM) was assessed for the three dimensional (3D) stacking of Si dice. In this process, solder bumps were deposited selectively onto the surface of a Cu plugged-through silicon-via (TSV) in a Si die. Since lithography related processes to make a PRM for solder bumping were omitted, it can reduce the production time and cost for bumping. The substrate was a Si wafer, and TSVs were produced by deep-ion-reactive-etching (DRIE). As an insulation layer, SiO 2 was formed by high-density-plasma-chemical-vapor-deposition (HDPCVD) or wet oxidation method. A Ti adhesion and an Au seed layers were deposited by sputtering. Cu was plugged into the vias by pulsed direct-current (DC) electroplating. The backside of the Si wafer was ground by chemicalmechanical-polishing (CMP). Sn bumps were electroplated on the Cu plugged vias by a current supplied through a Cu-overplated layer (COL) on the vias surface. As experimental results, wet oxidation provided a uniform SiO 2 thickness through the via depth, whereas the SiO 2 thickness by HDPCVD decreased with the via depth. The Ti and Au thicknesses also decreased along the via depth. In electroplating for Cu plugging, defect-free Cu plug was achieved by pulsed DC for 18 h, where one cycle composed of a 5 s cathodic term with À12:2 mAÁcm À2 and a 25 s anodic term with 2.3 mAÁcm À2 . Sn bumping using COL without PRM was accomplished successfully at a current density of À30 mAÁcm À2 for 15 min. The diameter and height of the Sn bumps ranged from 48.5 to 52 mm and 22 to 25 mm, respectively. The bumps had a rivet head shape without a columnar part and showed facets on the bump surface. The COL was removed by CMP without damage to the bumps.

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Low Electrical Resistance Silicon Through Vias: Technology and Characterization

Cited by 22 publications

References 5 publications

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Physical Design Issues in 3-D Integrated Technologies

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

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