Low energy FPGA interconnect design

Abstract

We propose a new low energy FPGA interconnect fabric that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study illustrates that the encoded-low swing technique and Dual Threshold MOS based switches results in 41% energy reduction compared to the conventional technique using full swing signalling and NMOS pass transistor based switches. We also show through a theoretical analysis, that a certain timing budget can be met by the EL technique, using 11% more buffered switches, but still consuming 62% less energy than conventional techniques. Circuit simulations, taking also the transmitter and receiver complexity into account, are in line with the model results and indicate that a timing budget can be met at 30% less energy consumption. All our results are based on CMOS 0.13µ process technology and are done using a transistor level simulator.

Designing a novel high-performance FPGA architecture for data intensive applications

“…Several approaches for designing high-performance reconfigurable devices by optimizing the interconnection architecture have been reported [3,4,8,12,17,[19][20][21][22], where some of them concerns the design of a non-homogeneous interconnection structure [12,20]. However, all of them pay effort to handle the parameters that affect the application delay (i.e.…”

“…More specifically: (1) increase of the propagation delay, (2) increase of the power and energy consumption, (3) increase of the silicon area, and (4) introduction of extra noise sources, affecting among others the device reliability. It is proven that the contribution of the interconnection network in FPGA delay and power consumption is very significant [3][4][5]21]. Consequently, the optimal design of the interconnection network should be the first design priority.…”

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

“…Several approaches for designing low-energy and/or high-performance FPGAs by optimizing the interconnection architecture has been reported [8], [12], [13], [11], [10], [9], [4], [3]. Among others, the design of non-homogeneous interconnection structure [13], [11], [4] and the use of multiple supply voltages, V DD , and/or multiple threshold voltages [10], [9], [3] were the main strategies, which have been chosen for achieving optimal FPGA designs.…”

“…Among others, the design of non-homogeneous interconnection structure [13], [11], [4] and the use of multiple supply voltages, V DD , and/or multiple threshold voltages [10], [9], [3] were the main strategies, which have been chosen for achieving optimal FPGA designs.…”