We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input

We propose a new low energy FPGA interconnect fabric that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study illustrates that the encoded-low swing technique and Dual Threshold MOS based switches results in 41% energy reduction compared to the conventional technique using full swing signalling and NMOS pass transistor based switches. We also show through a theoretical analysis, that a certain timing budget can be met by the EL technique, using 11% more buffered switches, but still consuming 62% less energy than conventional techniques. Circuit simulations, taking also the transmitter and receiver complexity into account, are in line with the model results and indicate that a timing budget can be met at 30% less energy consumption. All our results are based on CMOS 0.13µ process technology and are done using a transistor level simulator.

Abstract-We propose a new energy efficient method of designing switch blocks inside FPGAs using novel variations of the Dual Threshold CMOS (DTMOS) based switches instead of the conventional NMOS pass transistor or tri-state buffer based switches. By intelligently sharing the extra transistor needed for using DTMOS based switches, the area overhead is kept to a minimum. Sleep transistors are used to reduce sub-threshold leakage. Using our new, novel design, we obtain a 16% improvement in the power-delay product during the active mode per switch and a factor of 20 improvement in the stand-by mode, over conventional approaches. Extensive simulation results over benchmark circuits in CMOS 0.13µ are presented to illustrate the superiority of the proposed techniques. Since the proposed techniques target the switches and multiplexers which are present in large numbers on FPGAs, the overall improvement in the power-delay product is significant for an application implemented on a FPGA having the proposed features.