Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells

Rodbell, K. P.; Heidel, D.; Tang, H.H.K.; Gordon, Michael S.; Oldiges, Phil; Murray, Conal E.

doi:10.1109/tns.2007.909845

Cited by 170 publications

(69 citation statements)

References 8 publications

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“…For scaled, sensitive COTS parts, protons are able to generate enough charge through electronic stopping, called direct ionization, to cause soft errors. K. P. Rodbell et al [1] and D. F. Heidel et al [2] published the first demonstration of low-energy proton direct ionization soft errors in 2007 and 2008 for a commercial 65 nm silicon-oninsulator (SOI) CMOS process; the results from D. F. Heidel et al [3] are shown in Fig. 1.…”

Section: Low-energy Proton Soft Errorsmentioning

confidence: 99%

“…The spacecraft shielding distribution will determine which portion of the external proton energy spectrum becomes the low-energy spectrum that impacts sensitive microelectronic devices [2]. Low-energy protons have thus far been defined as protons with a kinetic energy less than 10 MeV, though energies that result in soft errors are typically below 2 MeV for the 65 and 45 nm process technologies documented thus far [1][2][3][4]. To be published in the 2010 International Reliability Physics Symposium conference proceedings.…”

Section: Low-energy Proton Soft Errorsmentioning

confidence: 99%

“…This is particularly true for commercial off the shelf (COTS) complementary metal oxide semiconductor (CMOS) parts. While these parts enable improved scientific investigations, evaluating the semiconductor technologies required for the missions creates unique testing challenges like the examination of low-energy proton-induced soft errors [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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Practicality of evaluating soft errors in commercial sub-90 nm CMOS for space applications

Pellish

LaBel

2010

2010 IEEE International Reliability Physics Symposium

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Abstract-Inclusion of commercial technologies in civil spaceflight applications is reality. These technologies enable higher performance, reduce power consumption, and ultimately yield better science. However, the benefits do not come without cost, and radiation-induced soft errors in advanced, sub-90 nm CMOS technologies present new challenges. These challenges include sensitivity to proton direct ionization, memory technology evaluation, as well as testing and evaluation complexity.

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Section: Low-energy Proton Soft Errorsmentioning

confidence: 99%

Section: Low-energy Proton Soft Errorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Practicality of evaluating soft errors in commercial sub-90 nm CMOS for space applications

Pellish

LaBel

2010

2010 IEEE International Reliability Physics Symposium

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“…The increasing chip power densities of SoCs allied to the continuous technology shrink are making SRAM cells more susceptible to soft errors, such as the ones caused by radiation e↵ects [2], particularly when it comes to neutron or alpha particles strikes [3,4]. Soft errors or Single Event Upset (SEU) induced by neutron may cause critical failures on system behaviour, which can lead to financial or human life losses [5].…”

Section: Introductionmentioning

confidence: 99%

Impact of dynamic voltage scaling and thermal factors on SRAM reliability

Rosa

Brum

Wirth

et al. 2015

Microelectronics Reliability

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This work investigates the e↵ects of temperature and voltage scaling in neutron-induced bit-flip in SRAM memory cells. Proposed approach allows determining the critical charge according to the dynamic behaviour of the temperature as a function of the voltage scaling. Experimental results show that both temperature and voltage scaling can increase in at least two times the susceptibility of SRAM cells to Soft Error Rate (SER). In addition, a model for electrical simulation for soft error and di↵erent voltages was described to investigate the e↵ects observed in the practical neutron irradiation experiments. Results can guide designers to predict soft error e↵ects during the lifetime of SRAM-based devices considering di↵erent power supply modes.

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“…As the energy threshold for causing an error decreases, the number of particles with sufficient energy increases rapidly [18]. For instance, at lower energy thresholds, even trace amounts of radioactive contaminants in solder can affect CMOS circuits [8].…”

Section: Introductionmentioning

confidence: 99%

Improving testability and soft-error resilience through retiming

Krishnaswamy

Markov

Hayes

2009

Proceedings of the 46th Annual Design Automation Conference

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State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking. Most prior methods of reducing the soft-error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects. Our work explores the fundamental relations between the SER of sequential circuits and their testability in scan mode, and appears to be the first to improve both through retiming. Our retiming methodology relocates registers so that 1) registers become less observable with respect to primary outputs, thereby decreasing overall SER, and 2) combinational nodes become more observable with respect to registers (but not with respect to primary outputs), thereby increasing scantestability. We present experimental results which show an average decrease of 42% in the SER of latches, and an average improvement of 31% random-pattern testability.

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Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells

Cited by 170 publications

References 8 publications

Practicality of evaluating soft errors in commercial sub-90 nm CMOS for space applications

Practicality of evaluating soft errors in commercial sub-90 nm CMOS for space applications

Impact of dynamic voltage scaling and thermal factors on SRAM reliability

Improving testability and soft-error resilience through retiming

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