Abstract-InAIAslInGaAs HFET's fabricated by conventional mesa isolation have a potential parasitic gate-leakage path where the gate metallization overlaps the exposed channel edge at the mesa sidewall. We have unmistakably proven the existence of this path by fabricating special heterojunction diodes with different mesa-sidewall gate-metal overlap lengths. We find that sidewall leakage is a function of the crystallographic orientation of the sidewall, and increases with channel thickness, sidewall overlap area, and InAs mole fraction in the channel. In HFET's fabricated alongside the diodes, sidewall leakage increased the subthreshold and forward gate leakage currents, and reduced the breakdown voltage. Fabrication of these HFET's by conventional mesa isolation, however, results in sidewalls where the InGaAs channel is exposed and comes in contact with the gate metallization running up the mesa (Fig. 1). Even though the sidewall contact area can easily be several orders of magnitude smaller than the gate area, the low Schottkybarrier height of metals with Ino,5,Gao,47As (0.2 eV) [6] potentially results in a significant leakage path from the gate to the channel. In AlGaAs/GaAs HFET's, mesasidewall gate leakage, or sidewall leakage for short,