Low-frequency Low-noise Transistors Fabricated by Double Ion Implantation

Abstract

A two-stage annealing process composed of first-stage low-temperature wet-oxygen oxidation and second-stage high-temperature dry-nitrogen drive in is proposed to fabricate double-implanted low-frequency low-noise npn transistors. Emitter edge dislocations and surface contaminations such as SiC particles are eliminated by the two-stage annealing process, and the double-implanted transistors having the equivalent noise voltage at 10 Hz of 12 nV/√Hz and the linearity in collector current dependence of h FE of 0.9–0.95 are achieved. Uniformity in h FE within ±5% are obtained by the optimization of first-stage low-temperature wet-oxygen oxidation process.