C e n t r a l R e s e a r c h L a b o r a t o r y , H i t a c h i L t d . , K o k u b u n j i , Tokyo 1 8 5 " T a ! ; a s a k i l s o r k s , H i t a c h i L t d . , T a k a s a k i , Gunma 3 7 0 -1 1 , J a p a n ABSTRACT S e c o n d -d u r a t i o n r a p i d -t h c r m . a l a n n e a li n n t e c h n i q u e i s a p p l i e d t o a n A s d r i v e -i n p r o c e s s f r o m a s t a c k e d CVD p o l y -S i f i l m f o r shallo!\l emitter f o r m a t i o n .

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A two-stage annealing process composed of first-stage low-temperature wet-oxygen oxidation and second-stage high-temperature dry-nitrogen drive in is proposed to fabricate double-implanted low-frequency low-noise npn transistors. Emitter edge dislocations and surface contaminations such as SiC particles are eliminated by the two-stage annealing process, and the double-implanted transistors having the equivalent noise voltage at 10 Hz of 12 nV/√Hz and the linearity in collector current dependence of h FE of 0.9–0.95 are achieved. Uniformity in h FE within ±5% are obtained by the optimization of first-stage low-temperature wet-oxygen oxidation process.

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