Low-frequency noise characteristics in SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS)

Abstract

We present the first investigation of low frequency noise in the SiGe channel heterostructure dynamic threshold p-MOSFET (HDTMOS). The sub-threshold characteristics and drain current noises were measured and evaluated. The input referred noise of the SiGe HDTMOS was reduced to about one-tenth compared with that of the Si MOS, because of higher transconductance g, and less interface states at the Si/SiGe hetero-interface.

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

“…( 14), and therefore allows for examination other factors and scaling rules that impact the 1/f noise and for comparisons between devices, technologies and so on, as has been illustrated in Figure 20 , at specified bias condition for FOM S VG . (247) Note that the bias dependence of the noise is neglected in FOM S VG at an assumption that the bias dependence of the noise in relative units is similar in different MOS transistors, and also, it is assumed that the only one size dependence is the scaling rule with the reciprocal of the area of otherwise identical devices and the noise is exactly 1/f. Evidently from the discussions in preceding sections, the bias, frequency and size dependences vary several decades, and the models are devoted to capture these dependences.…”

“…Qualitatively, the channel depth in pMOS transistor is depicted in the right-hand plots of Figure 43 for reverse, zero and forward body bias (plots from top to bottom) at similar charge sheet concentrations (the dotted shapes for the charge carrier layers denote same area). Quantitative examples for the charge concentrations in Si and SiGe MOS transistors can be found in [247]. To the best of our knowledge, there is no 1/f noise model for MOS transistors that considers the volume distribution of the carriers in the depth of the channel, which can possibly explain the body bias dependence with variation of current density in terms of Hooge noise in its integral form of eq.…”

Silicon on Insulator Technology Review

“…These effects certainly will not [92,84,29]prevent the widespread adoption of SOI for CMOS ICs, but they must be taken into account by thoughtful device and circuit design approaches that specifically address the peculiarities of the SOI CMOS transistor vs. the bulk or epitaxial wafer CMOS transistor.…”

Temperature Stability of Dynamic-Threshold Mode SiGe p-Metal–Oxide–Semiconductor Field Effect Transistors

“…On the other hand, the onset of heavy inversion for strained SiGe pMOSFETs occurs at a smaller gate voltage and is less F -dependent since a large valence-band offset at the Si/Si 1Àx Ge x interface leads to a good hole confinement within the buried SiGe channel and consequently, less gatecontrolled depletion charges as well as a smaller vertical electric field in the substrate. 3,4) This explains why V TH of SiGe MOSFETs is smaller and less sensitive to temperature, which is very important for practical integrated circuit applications since digital VLSI circuits often operate at elevated temperatures due to heat generation. The substrate sensitivity is an important factor for DT-MOSFETs since a larger substrate sensitivity implies that better drive current and suppressed short channel effects could be benefit from it.…”