Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

Abstract

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n-and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f ) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 ' 10 7 for n-type and 2 ' 10 6 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (V th ) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control V th more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L gate WS Id =I 2 d of 10 %13 -10 %11 µm 2 /Hz for n-type and 10 %12 -10 %10 µm 2 /Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET

“…The model value that is shown by the dashed line is in good agreement with the measured value, which is shown by the solid line. Since the models are experimentally extracted from the actually fabricated 60 nm vertical BC MOSFETs, 16) the model can be applied to simulate power supply circuits with rough credibility close to actual measurement. BSIM4 models were also used for other prior research studies on power supply circuits.…”

“…[9][10][11][12][13][14][15][16][17][18][19][20] Figure 2 shows a bird's-eye view of a single-pillar-type vertical BC MOSFET. The vertical BC MOSFET arranges the source, gate and drain vertically.…”

Highly Efficient and Compact CMOS DC-DC Converter with Novel Transistor Layout of 60 nm Multi-pillar Type Vertical Body Channel MOSFET

“…Table I. The applied MOSFET model is extracted from the experimental data of Vertical BC MOSFET with the 60 nm diameter and 100 nm gate length [5]. Fig.…”

Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise

“…Imamoto et al [19], Forbes and Miller [20], Chen et al [21], Ioannidis et al [22], Pirro et al [23] have tried to decrease the level of RTN noise by changing some parameters in the structure of MOSFET devices. Although these methods can be effective, they might be so expensive.…”