Low-Jitter Frequency Generation Techniques for 5G Communication: A tutorial

Wu, Wanghua

doi:10.1109/mssc.2021.3111430

Cited by 16 publications

(6 citation statements)

References 68 publications

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“…signal in supporting the complex modulation schemes (e.g., 256-or 1024-QAM) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12]. At the same time, with the signal bandwidths reaching 800 MHz in the 5G mm-wave bands, direct conversion transmitters and receivers are preferred.…”

Section: Table I Specifications Of Irr and Its Corresponding Evmmentioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90 • I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140-250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors' knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

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Section: Table I Specifications Of Irr and Its Corresponding Evmmentioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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“…Since the phase of the frequency-tunable oscillator cannot be corrected immediately, t corr [k] calculated at the end of nth reference cycle (i.e., k = nN) will not be visible until at least the next oscillator cycle. 3 Thus, a loop delay of z −L osc (L ≥ 1) is introduced between t corr [k] and t osc [k]. L is an integer here, readily estimated by inspection (or a quick simulation) of the PLL structure.…”

Section: Multirate Timestamp Models a Multirate Timestamp Model Of Hi...mentioning

confidence: 99%

“…Replacing I cp with A 0 2π f osc • g m • τ pulse , the SS-PLL's [4] model could be obtained. 3 For further details, refer to the DCO's timestamp's model in Verilog-AMS on [44, p. 74] (the model can accept an asynchronous change at the frequency/period-tuning input within an oscillator cycle and execute it at the next oscillator cycle). 4 For example, if N = 49 or 50, the updated t corr [k] is assumed appearing at the 26th T osc within the reference cycle (i.e., L = 26).…”

Section: ) Adc-based Tdcmentioning

confidence: 99%

“…A FREQUENCY synthesizer of ultra-low jitter (i.e., sub-50 fs) is a key block to enable the emerging 5G/6G wireless and other high-speed communication standards [1]- [3]. There are two main routes being pursued towards achieving such tough jitter performance: high-bandwidth PLLs with a high phase-detector (PD) gain [4]- [14], and injection-locking (IL) [15]- [24] or a recently introduced generalization of it, charge-sharing locking (CSL) [2], [25].…”

Section: Introductionmentioning

confidence: 99%

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Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

Siriburanon

Staszewski

2022

IEEE Trans. Circuits Syst. II

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In this tutorial brief, we introduce a unified wideband phase-noise theory framework of frequency synthesis based on a multirate timestamp modeling with "two z-variables". We apply it to model and analyze two types of ultra-low jitter (i.e., sub-50 fs) phase-locking techniques: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL), serving as a unified guide on achieving the sub-50 fs jitter. All analytical results are numerically verified through time-domain behavioral simulations, demonstrating that the theoretically maximum bandwidths are around 30% and 44% of the reference frequency in PLLs and IL, respectively.

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“…For most of wireline and wireless applications, normalized jitter, the ratio of jitter over one clock cycle (or one bit period), is one of the major limiting factors that limiting the bit-error rate (BER) [161], [162]. For example, a 1-GHz clock with 1-ps RMS jitter is equivalent to a 2-GHz clock with 0.5-ps RMS jitter, in terms of BER.…”

Section: E Clock Frequency Scalingmentioning

confidence: 99%

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Bae

2022

IEEE Access

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A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a few assumptions, theoretically, it provides a fair comparison. However, as the PLL design techniques have advanced, the assumptions have started breaking. Also, it misses performance impacts from some other important factors other than the jitter and the power. As a result, it is expected that the performance comparison with the conventional FOM is not fair enough for some cases. This work reviews the state-of-the-art PLL design techniques and investigates how those techniques conflict with the assumptions of the conventional FOM. In addition, alternate FOMs which complement the conventional FOM are discussed. To capture complex cross-correlation between various factors, the proposed methodology is to find a correlation between the conventional FOM and other factors from extensive performance surveys, along with quantitative analyses.

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Low-Jitter Frequency Generation Techniques for 5G Communication: A tutorial

Cited by 16 publications

References 68 publications

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

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