“…16 illustrates, 30 ns of dead time result in a THD of ≈ -100 dB over a wide load current range. Such low dead times are facilitated by the fast half-bridge switching transitions, which take less than 6 ns at a DC-link voltage of 400 V [23]. As the high-side half-bridge power transistor requires an isolated gate control signal, the propagation delay difference (skew) of the two half-bridge gate control signal paths (and the variation of this timing difference, e.g., due to temperature), which is mostly dominated by the digital signal isolators, imposes a practical lower limit to dead time, as it must be guaranteed that a minimum dead time is always ensured to prevent halfbridge shoot-through.…”