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Abstract-An improved gate driver is presented which significantly lowers the output noise of high-precision switch-mode (Class-D) power amplifiers by reducing signal jitter at the output of the power stage tenfold to values below 20 ps. Gate signal jitter in power electronic converters, which introduces wideband noise to the power output, originates mainly from the signal isolators that are required to provide the galvanically isolated gate driver control signals. A low-jitter gate control signal is produced by employing a digital flip-flop, which uses a low-jitter isolated clock, to re-synchronize the jittery gate control signal. By utilizing the clock-enable input of the flip-flop, the gate driver can be rendered immune to high-speed common-mode transients, which is important as the Class-D power amplifier demonstrator system employs fast-switching GaN E-HEMT transistors, where the 400 V switching transients exceed 300 kV µs −1 . The signal to noise ratio of a sinusoidal output signal is measured at 107 dB, which is an improvement of ≈20 dB as compared to the performance of a conventional gate driver.Index Terms-Low-jitter gate driver, common-mode transient immunity (CMTI), low noise switch-mode power amplifier, wide-bandgap gallium nitride power semiconductors, signal to noise ratio (SNR)