Low Latency FPGA Implementation of Izhikevich-Neuron Model

Abstract

The Izhikevich's simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are powerful, flexible, and inexpensive digital hardware that can implement such model. In this paper, we present a highly combinational, low latency implementation of ISM for FPGA. In the absence of official benchmark to compare different implementations, we propose two different metrics to compare the technical literature with our implementation. In this benchmark, we can implement a system that, when compared to the literature, has almost 1.5 times the number of digital neurons (DN), and latency more than 56 times smaller. This shows that our implementation is best suited for hybrid network systems and presents a fair performance for only-artificial networks.

A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA

“…The hardware implementation presented in [21] focuses on studying fully-connected neural networks; their real-time emulator targets closed-loop experiments, and it is hosted by a Xilinx Virtex-6 FPGA. The system implements 1,440 Izhikevich neurons with a resolution of 0.1 ms and a spike latency of 1 ms. Other studies focus on more specific problems, such as minimizing the neurons emulation latency down to 8 ns to increase the maximum number of neurons that can be emulated in a single FPGA chip, at the expense of the biological meaning [22]. This result has been achieved by designing a systolic array to integrate a simplified version of the Izhikevich neural model.…”

“…Luo et. al [24] propose a Network on Chip (NoC) hardware architecture, implemented on a Xilinx Virtex-7 FPGA, capable of emulating 101,000 LIF neurons [20] and 100,000 synapses in closed- [20] 2018 Xilinx Kintex-7 12,800 2.00e4 Pani [21] 2017 Xilinx Virtex-6 1,440 2.07e6 Bandeira [22] 2017 Altera Stratix IV 364 3.64e2 Luo [24] 2016 Xilinx Virtex-7 101,000 1.00e5 Ambroise [26] 2013 Xilinx Virtex-4 117 1.37e4 Han [9] 2020 Xilinx Kintex-7 [26], and a higher number of synapses in general. In fact, the presented work has been conceived as a tool to study the behaviors of biological neural networks, rather than a machine learning accelerator.…”

“…Moreover, our work requires only the 43.80% of the LUTs, the 72.49% of the FFs, the 33.29% of the BRAMs, and the 34.31% of the DSPs compared to the implementation in [21]. The low-latency neural network accelerator presented in [22] is implemented on a Stratix-IV device, and can sustain a maximum clock frequency of 250 MHz. This allows to integrate the Izhikevich model in 8 ns and reuse many times the same neuron computational core within their 0.78 ms integrating step, as it happens in the presented work.…”

“…However, the throughput of our Potential module guarantees an integrated neuron every 6 ns, which is higher than 8 ns, even though our maximum clock frequency is lower. In addition, the neuron interconnections scheme of this work has more biological meaning than in [22], where the neurons can have a single synaptic interconnection. The maximum number of neuron computational cores which fit in the Stratix-IV device is 364, but it is not explicitly declared the maximum number of neurons their architecture can handle in real-time.…”