Low-latency Hardware Architecture for VDF Evaluation in Class Groups

Zhu, Dong; Tian, Jing; Li, Minghao; Wang, Zhongfeng

doi:10.1109/tc.2022.3219723

Cited by 2 publications

(8 citation statements)

References 27 publications

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“…One complete reduced squaring in the class group requires a squaring and a reduction operation. For squaring operation, one option is to use the squaring algorithm summarized in [Lon18], which is also the algorithm adopted by [ZTLW22], and another is to use the NUDUPL algorithm which is the algorithm adopted in this work. For these two algorithms, the computation time required and the ratio of computation time of squaring are different.…”

Section: Implementation Results and Discussionmentioning

confidence: 99%

“…5, the NUDUPL algorithm takes up almost all time for the squaring, so the design of NUDUPL is much more important than the design of reduction. We chose the reduction design in [ZTLW22] to obtain a complete hardware simulation result. We coded the overall design and run the code on the EDA platform for simulation.…”

Section: Implementation Results and Discussionmentioning

confidence: 99%

“…The design was implemented in ASIC, and the implementation results show that it is 8x faster than the XGCD implementation in Zhu's work [ZST + 20]. Recently, complete hardware implementation for the VDF evaluation in the class group was proposed in [ZTLW22] which achieves a 3.6x speedup compared to the C++ implementation result. This design chose the standard squaring algorithm rather than the more efficient NUDUPL algorithm, and a modified parallel XGCD algorithm was used for XGCD calculation.…”

Section: Related Workmentioning

confidence: 99%

“…Since the VDF application has only been proposed for a short time and is computationally complex, the results of the hardware implementation are still limited. The works in [ZTLW22] and [SHT22] are implementations of XGCD in VDF, and [ZST + 20] did not implement the reduction. Among these previous works, only that of [ZTLW22] is a complete implementation for the squaring in the class group, but the algorithm and the hardware design in it can be greatly optimized.…”

Section: Contributionsmentioning

confidence: 99%

“…The works in [ZTLW22] and [SHT22] are implementations of XGCD in VDF, and [ZST + 20] did not implement the reduction. Among these previous works, only that of [ZTLW22] is a complete implementation for the squaring in the class group, but the algorithm and the hardware design in it can be greatly optimized. Compared to these work, we propose a low-latency implementation for the VDF in class groups with a 2048-bit discriminant by using an efficient NUDUPL algorithm for the first time.…”

Section: Contributionsmentioning

confidence: 99%

See 4 more Smart Citations

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation

Zhu

Zhang

et al. 2022

TCHES

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A verifiable delay function (VDF) is a function whose evaluation requires running a prescribed number of sequential steps over a group while the result can be efficiently verified. As a kind of cryptographic primitives, VDFs have been adopted in rapidly growing applications for decentralized systems. For the security of VDFs in practical applications, it is widely agreed that the fastest implementation for the VDF evaluation, sequential squarings in a group of unknown order, should be publicly provided. To this end, we propose a possible minimum latency hardware implementation for the squaring in class groups by algorithmic and architectural level co-optimization. Firstly, low-latency architectures for large-number division, multiplication, and addition are devised using redundant representation, respectively. Secondly, we present two hardware-friendly algorithms which avoid time-consuming divisions involved in calculations related to the extended greatest common divisor (XGCD) and design the corresponding low-latency architectures. Besides, we schedule and reuse these computation modules to achieve good resource utilization by using compact instruction control. Finally, we code and synthesize the proposed design under the TSMC 28nm CMOS technology. The experimental results show that our design can achieve a speedup of 3.6x compared to the state-of-the-art implementation of the squaring in the class group. Moreover, compared to the optimal C++ implementation over an advanced CPU, our implementation is 9.1x faster.

show abstract

Section: Implementation Results and Discussionmentioning

confidence: 99%

Section: Implementation Results and Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Contributionsmentioning

confidence: 99%

Section: Contributionsmentioning

confidence: 99%

See 3 more Smart Citations

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation

Zhu

Zhang

et al. 2022

TCHES

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Research on blockchain smart contract technology based on resistance to quantum computing attacks

Zheng

2024

PLoS ONE

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In recent years, blockchain technology has developed rapidly and has been widely used in medical, financial, energy and other fields. However, in the process of practical application, each blockchain is a small independent ecosystem, with all transactions and operations limited to the chain, resulting in a large number of mutually heterogeneous to independent blockchains. It presents challenges for cross-chain interactions, cross-organization data sharing, and cross-blockchain expansion, and hinders the wider application of blockchain technology. In addition, the traditional digital signature method based on elliptic curve cipher faces the threat of being cracked by quantum computing attacks. To solve the aforementioned problems, this paper proposed a blockchain smart contract technique based on quantum computing attack resistance(BSCTQCAT). The technique first introduces the digital signature of the lattice cipher into the blockchain to resist the quantum search algorithm attack. Then, based on the smart contract authentication scheme, the nodes on multiple heterogeneous chains are organized into an identity agent layer P2P network, through which transactions on the chain will establish a credible identity management and message authentication mechanism between different chains, solving the current problem that each chain is difficult to communicate with each other. In this paper, the performance of the algorithm is evaluated by simulating the Bitcoin transaction scenario and analyzing the experimental data.

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Low-latency Hardware Architecture for VDF Evaluation in Class Groups

Cited by 2 publications

References 27 publications

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation

Research on blockchain smart contract technology based on resistance to quantum computing attacks

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