Low Leakage Current of Liquid Phase Deposited SiO[sub 2]∕TiO[sub 2 ] Stacked Dielectrics on (NH[sub 4])[sub 2]S-Treated InP

Abstract

The characteristics of a metal-oxide-semiconductor ͑MOS͒ capacitor with liquid phase deposited SiO 2 /TiO 2 stacked dielectrics on p-type ͑NH 4 ͒ 2 S-treated InP͑100͒ were investigated. The leakage currents of an InP MOS capacitor with TiO 2 as a dielectric are 1.66 ϫ 10 −7 and 6.83 ϫ 10 −7 A/cm 2 at Ϯ0.5 MV/cm, respectively. The leakage current is mainly from the thermal ionic emission. The dielectric constant is 43.4. With the deposition of 3 nm high bandgap SiO 2 on TiO 2 as stacked dielectrics, the leakage current can be improved to 2.14 ϫ 10 −9 and 6.43 ϫ 10 −9 A/cm 2 at Ϯ0.5 MV/cm, respectively. The dielectric constant is 29.5. Due to high electron mobility and direct energy bandgap compared with Si, much attention has been focused on indium phosphide ͑InP͒ high-speed and optoelectronic devices. Currently, the metal-semiconductor field effect transistor ͑MESFET͒ is the main structure of InP high-speed devices. The main disadvantage of MESFET is the high gate current of Schottky contact under the positive bias of several tenths of a volt, which severely limits the maximum drain current, the noise margin, and the flexibility of the circuit design. Compared with MESFET, the gate insulating layer of a metal-oxide-semiconductor field effect transistor ͑MOSFET͒ can improve these disadvantages.Usually, the high density of interface states ͑D it ͒ is the major problem of a III-V compound semiconductor MOSFET, which causes the pinning of the surface Fermi level near the middle of the energy gap. 1 The native oxides cause the high D it ͑Ref. 2͒ and a poor interface quality. The improvement of the electrical properties of the semiconductor was attributed to the removal of the surface native oxides and the covering of the surface with sulfur atoms. 3 It was reported that ͑NH 4 ͒ 2 S or ͑NH 4 ͒ 2 S x solution can thoroughly remove the surface oxide on InP ͑Ref. 4͒ and improve the electrical properties of enhancement mode field-effect-transistor. 5,6 Four unit cells of titanium dioxide ͑TiO 2 ͒ in ͓110͔ direction match well with three unit cells of InP in ͑100͒ plane ͑1.2% lattice mismatch͒. 7 An amorphous layer can reduce the leakage current of the polycrystalline grain boundaries. Amorphous is a short range crystalline. The lattice match between the amorphous TiO 2 and InP will reduce the density of dangling bonds locally and hence the interface states. Therefore, TiO 2 /InP would have a lower D it . 7,8 In addition, TiO 2 is a high dielectric constant ͑high-k͒ material ͑k value 35-100͒, 9,10 and a high transconductance of MOSFET with TiO 2 as the gate oxide is expected. 11 The chemical vapor deposition is the major technique used for preparing high quality polycrystalline TiO 2 films. 12,13 The leakage current of TiO 2 metal-oxide-semiconductor ͑MOS͒ capacitor is high due to the interface state at TiO 2 /InP and the grain boundary of TiO 2 film. For the high temperature process for TiO 2 growth, it will degrade the passivation function of the ͑NH 4 ͒ 2 S treatment. Therefore, a low temperature TiO 2 growth process is ...

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