Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications

Subramanian, Vivek; Toita, Masato; Ibrahim, Nour; Souri, S.J.; Saraswat, Krishna C.

doi:10.1109/55.772370

Cited by 61 publications

(34 citation statements)

References 6 publications

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“…12,13 In a previous article, we reported a new low-temperature ͑500°C͒ ␣-Si crystallization phenomenon that occurs at the perimeter of a Ge layer grown on ␣-Si through a window in a SiO 2 layer.…”

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confidence: 99%

“…12,13 Improved values of mobility were obtained for thin-film transistors fabricated in ␣-Si layers crystallized using a germanium seed. 12,13 In a previous article, we reported a new low-temperature ͑500°C͒ ␣-Si crystallization phenomenon that occurs at the perimeter of a Ge layer grown on ␣-Si through a window in a SiO 2 layer. 14 This phenomenon was termed perimeter crystallization and the results suggested the presence of an additional crystallization mechanism in the early stages of the crystallization process.…”

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confidence: 99%

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Mechanism of Germanium-Induced Perimeter Crystallization of Amorphous Silicon

Hakim

Ashburn

2007

J. Electrochem. Soc.

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We report a study aimed at highlighting the mechanism of a new amorphous silicon crystallization phenomenon that originates from the perimeter of a germanium layer during low-temperature annealing ͑500°C͒. Results are reported on doped and undoped amorphous silicon films, with thicknesses in the range 40-200 nm, annealed at a temperature of 500 or 550°C. A comparison is made of crystallization arising from Ge and SiGe layers and the role of damage from a high-dose fluorine implant is investigated. Plan-view scanning electron microscope images show that perimeter crystallization is only present in amorphous silicon films with thicknesses ഛ100 nm, and that the crystallization width increases with decreasing film thickness and increasing doping level. Cross-sectional scanning electron microscope images show that the perimeter crystallization originates from grains at the bottom of the amorphous silicon film. The perimeter crystallization phenomenon disappears when the amorphous silicon is implanted with fluorine and when an Si 80% Ge 20% layer is employed instead of germanium. The perimeter crystallization is due to the formation of large grains as a result of an increased growth rate of pre-existing grains and this is attributed to the strain generated by the thermal expansion of the germanium layer during anneal. The crystallization of amorphous silicon ͑␣-Si͒ has been intensively investigated for application in active-matrix flat-panel displays and 3D electronics.1-10 Several techniques have been studied for the fabrication of high-quality polycrystalline silicon ͑poly-Si͒ with large crystallite size, low grain-boundary defect density, and high carrier velocity. These include excimer laser crystallization ͑ELC͒, 1-3 solid-phase crystallization ͑SPC͒, 4,5 metal-induced crystallization ͑MIC͒, 6,7 and metal-induced lateral crystallization ͑MILC͒. [8][9][10] This latter approach has the advantage of giving good control over the location of the grain boundaries but the disadvantage of introducing metal contamination into the ␣-Si, with deleterious effects on transistor performance. 11Germanium has also been proposed as a seeding agent for the lateral crystallization of ␣-Si 12,13 because of its better compatibility with scaled complementary metal oxide semiconductor ͑CMOS͒ technology. The lower melting point of germanium than silicon was reported to reduce the incubation time for the crystallization of the underlying amorphous silicon film by the formation of a SiGe layer at the Ge-Si interface.12,13 Improved values of mobility were obtained for thin-film transistors fabricated in ␣-Si layers crystallized using a germanium seed. 12,13 In a previous article, we reported a new low-temperature ͑500°C͒ ␣-Si crystallization phenomenon that occurs at the perimeter of a Ge layer grown on ␣-Si through a window in a SiO 2 layer.14 This phenomenon was termed perimeter crystallization and the results suggested the presence of an additional crystallization mechanism in the early stages of the crystallization process. Perimeter c...

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confidence: 99%

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confidence: 99%

Mechanism of Germanium-Induced Perimeter Crystallization of Amorphous Silicon

Hakim

Ashburn

2007

J. Electrochem. Soc.

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“…The lower melting point of germanium than that of silicon was reported to reduce the incubation time for the crystallization of the underlying amorphous silicon film by the formation of a SiGe layer at the Ge-Si interface. 12,13 Atomic force microscopy and transmission electron microscopy ͑TEM͒ showed increased amorphous silicon crystallization underneath the germanium seed compared with unseeded areas. 12,13 Improved mobility values were obtained for thin film transistors fabricated in ␣-Si layers crystallized using a germanium seed.…”

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confidence: 99%

“…12,13 Atomic force microscopy and transmission electron microscopy ͑TEM͒ showed increased amorphous silicon crystallization underneath the germanium seed compared with unseeded areas. 12,13 Improved mobility values were obtained for thin film transistors fabricated in ␣-Si layers crystallized using a germanium seed. 12,13 In this article we report a new ␣-Si crystallization phenomenon that occurs at the perimeter of a germanium seed during an anneal at 500°C.…”

mentioning

confidence: 99%

“…12,13 Improved mobility values were obtained for thin film transistors fabricated in ␣-Si layers crystallized using a germanium seed. 12,13 In this article we report a new ␣-Si crystallization phenomenon that occurs at the perimeter of a germanium seed during an anneal at 500°C. This perimeter crystallization phenomenon contrasts with the behavior observed during a 550°C anneal where an increased crystallization is seen in all regions beneath the germanium seed, as reported previously.…”

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Perimeter Crystallization of Amorphous Silicon around a Germanium Seed

Hakim¹,

Maťko²,

Chenevier³

et al. 2006

Electrochem. Solid-State Lett.

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Wafer Level 3-D ICs Process Technology

Tan¹,

Gutmann²,

Reif³

2008

Integrated Circuits and Systems

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Monolithic three-dimensional integrated circuits (3D ICs) -defined here to be ICs in which circuit elements are fabricated on a substrate, and at least one layer above this substrate, in a single linear process flow with no material bonding requiredwere first touted in the literature in the early 1980s as a way to get around what were then perceived as scaling limits in silicon complementary metal-oxide semiconductor (CMOS) devices. Moreover, monolithic 3D ICs were envisioned as one way to reduce interconnect delay bottlenecks in 2D ICs [1].However, conventional 2D CMOS devices have consistently been scaled beyond all these perceived limits; thus, simply scaling CMOS circuits has been more cost-effective than building-in the third dimension. There have been exceptions: polyload static random access memories (SRAMs), for example, where the elements placed in the third dimension are as simple (and as cheaply made) as possible.Recently, the amount of interest in monolithic 3D ICs has been increasing, again driven by the increasing difficulty and expense of scaling silicon devices and technologies. It is thus worth reviewing some of the previously introduced stacking methods, as well as examining in detail the current technologies and their applications.In this chapter, we will begin by discussing the device-stacking schemes using large-grained polysilicon (>∼5 m), which are applicable especially for CMOS logic circuits. We will review the different crystallization techniques for the upper layers of these stacked circuits, as well as the process integration for these schemes. We will then consider techniques using small-grained polysilicon for the upper devices; these are applied mostly for memory devices. Finally, we will provide a short synopsis on monolithic techniques for non-silicon devices.

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Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications

Cited by 61 publications

References 6 publications

Mechanism of Germanium-Induced Perimeter Crystallization of Amorphous Silicon

Mechanism of Germanium-Induced Perimeter Crystallization of Amorphous Silicon

Perimeter Crystallization of Amorphous Silicon around a Germanium Seed

Wafer Level 3-D ICs Process Technology

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