Wafer Level 3-D ICs Process Technology

Abstract

Monolithic three-dimensional integrated circuits (3D ICs) -defined here to be ICs in which circuit elements are fabricated on a substrate, and at least one layer above this substrate, in a single linear process flow with no material bonding requiredwere first touted in the literature in the early 1980s as a way to get around what were then perceived as scaling limits in silicon complementary metal-oxide semiconductor (CMOS) devices. Moreover, monolithic 3D ICs were envisioned as one way to reduce interconnect delay bottlenecks in 2D ICs [1].However, conventional 2D CMOS devices have consistently been scaled beyond all these perceived limits; thus, simply scaling CMOS circuits has been more cost-effective than building-in the third dimension. There have been exceptions: polyload static random access memories (SRAMs), for example, where the elements placed in the third dimension are as simple (and as cheaply made) as possible.Recently, the amount of interest in monolithic 3D ICs has been increasing, again driven by the increasing difficulty and expense of scaling silicon devices and technologies. It is thus worth reviewing some of the previously introduced stacking methods, as well as examining in detail the current technologies and their applications.In this chapter, we will begin by discussing the device-stacking schemes using large-grained polysilicon (>∼5 m), which are applicable especially for CMOS logic circuits. We will review the different crystallization techniques for the upper layers of these stacked circuits, as well as the process integration for these schemes. We will then consider techniques using small-grained polysilicon for the upper devices; these are applied mostly for memory devices. Finally, we will provide a short synopsis on monolithic techniques for non-silicon devices.

Ti/Si interface enabling complementary metal oxide semiconductor compatible, high reliable bonding for inter-die micro-fluidic cooling for future advanced 3D integrated circuit integration

“…Over the years, the scaling in device dimensions of planar integration by following Moore's law resulted in an increased power density which leads to performance degradation due to the thermal issues, also the lithographic challenges triggered by fine pitch wiring where its scaling is much higher in comparison to transistor device scaling results in increased complexity of on-chip communication and manufacturing cost for finer nodes [1][2][3][4]. In particular, the 3D integrated circuit (IC) package with through-silicon via (TSV) heterogeneous integration enabled by the vertical interconnection of multiple electronic functional dies, will make shortened interconnects between different functional dies, allowing shortened interconnects between different functional dies, resulting in reduced power consumption and improved signal bandwidth at the same technology node compared to 2D ICs.…”