Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines

Arsovski, Igor; Nadkarni, Rahul

doi:10.1109/cicc.2005.1568702

Cited by 5 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, m can be approximated using circuit simulations. The I d,total current is directly related to n at (2) and therefore is affected by the number of mismatch cells. The change in I d,total by the number of mismatch cells is the important factor that determines the ground bounce voltage.…”

Section: A the Number Of Mismatch Cells And Ground Bouncementioning

confidence: 99%

“…CAM can produce comparison results in fixed intervals, regardless of the amount of words. The high-speed search operation in CAM is typically achieved at the cost of high power consumption as well as much instantaneous current demand [1], [2].…”

Section: Introductionmentioning

confidence: 99%

“…The search line delivers the search data pair to each comparison cell where the delivered data and the data stored in the comparison cell are compared [1], [3]. The search lines and match lines are constructed with long metal wires, which results in a large capacitance [2]. Significant power is consumed because of the voltage changes of the wires in all words at every clock cycle.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations

Jung

Baeg

Wen

et al. 2011

2011 12th International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

CAM devices generate excessive and simultaneous current through NOR circuits during a comparison operation because of the parallel comparisons for all bits in the CAM. The ground bounce noise can be severe due to the parasitic inductance in the paths to the system ground, such as the metal lines in the CAM power structure, package pins, and system board. The ground bounce noise can cause subtle failures unless carefully considered as a key design parameter. The simultaneous current largely depends on the number of stored bits matching compared data. Traditionally, the NOR circuit in the CAM is perceived to respond faster when the transistors to the ground path in the circuit are active. However, this work shows that this notion can be greatly misleading when the ground bounce effects are not considered.The design method of the comparison cells is newly proposed to meet the optimal CAM evaluation time by simultaneously considering operational speed, extreme case analyses of the NOR circuit, and ground bounce noises. The proposed design method effectively provided the optimal design decision, which could be otherwise misleading if no ground bounce effect is considered. We demonstrated in sample designs that the proper choice of comparison-cell size reduced evaluation time by 54.9% while reducing comparison-cell size by 57.1% when ground bounce effects were considered.

show abstract

Section: A the Number Of Mismatch Cells And Ground Bouncementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations

Jung

Baeg

Wen

et al. 2011

2011 12th International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

show abstract

“…The power dissipated by the former two components has effectively been reduced [2], [3], but the SLs still contribute 54%-82% to the total power consumption [1]. The SL power consumption can be reduced by using the segmented [1] or hierarchical SL scheme [4]- [6] and minimizing the switching activity [7], [8]. However, they suffer from either performance penalty or complex control circuitry.…”

Section: Introductionmentioning

confidence: 99%

A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup

Chang

2009

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

In this brief, we propose a two-level don't-care gating (DCG) scheme that aims to reduce the ternary content-addressable memory (TCAM) power dissipated in the search-line switching activity. By exploiting the vertically continuous "don't-care" feature, the two-level DCG scheme can largely reduce the average search-line power consumption during a switch pattern. In addition, we also use the search enable technique to eliminate the unnecessary search-line switching activity in the quiet pattern. By reducing both the search-line switching activity and average switching power, the proposed design can minimize the TCAM search-line power consumption. For a 128 x 32 TCAM, the best configuration we examined shows that when the first-level and second-level gating granularities are 16 and 8, respectively, with a 9% search performance improvement, the two-level DCG scheme can achieve 70% search-line energy reduction

show abstract

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

Arsovski¹,

Hebig

Dobson

et al. 2013

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines

Cited by 5 publications

References 5 publications

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations

A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

Contact Info

Product

Resources

About