Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

Singh, Anil; Rawat, Veena; Agarwal, Alpana

doi:10.1049/iet-cds.2016.0525

Cited by 3 publications

(2 citation statements)

References 26 publications

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“…An inverter-based integrator with auto-zeroing offset cancellation mechanism is shown in Fig. 2 [11] . In the clk1 phase, the inverter forms a unity-gain feedback circuit, and V off is sampled into capacitor C c .…”

Section: Circuit Principlementioning

confidence: 99%

A 0.6-V, 69-dB subthreshold sigma–delta modulator

Chen

Zhang

2018

J. Semicond.

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In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma–delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier (OTA), the sigma–delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13 μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.

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Section: Circuit Principlementioning

confidence: 99%

A 0.6-V, 69-dB subthreshold sigma–delta modulator

Chen

Zhang

2018

J. Semicond.

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“…Another common approach is to adopt low-gain op-amp and digital calibration technique to resolve the nonlinearity issue arise (Chiang et al, 2014;Singh et al, 2017). Verma and Razavi (2009) in their work used least mean square (LMS) engine to adjust stage gain coefficient and op-amp linearity.…”

Section: Introductionmentioning

confidence: 99%

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

Idros

Aziz

Rajendran

2020

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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Fast digital foreground gain error calibration for pipelined ADC

Kaur¹,

Prabhakar

Singh

et al. 2019

IET Circuits, Devices & Systems

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Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue-to-digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix-7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non-linearity improves by 30% and integral non-linearity reduces from values +60/−60 LSB to +0.77/-0.77 LSB. Also, signal to noise and distortion ratio and spurious-free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration.

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Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

Cited by 3 publications

References 26 publications

A 0.6-V, 69-dB subthreshold sigma–delta modulator

A 0.6-V, 69-dB subthreshold sigma–delta modulator

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

Fast digital foreground gain error calibration for pipelined ADC

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Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

Cited by 3 publications

References 26 publications

A 0.6-V, 69-dB subthreshold sigma–delta modulator

A 0.6-V, 69-dB subthreshold sigma–delta modulator

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

Fast digital foreground gain error calibration for pipelined ADC

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Product

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A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier