Low-power 3D graphics processors for mobile terminals

Sohn, Ju-Ho; Park, Yong-Ha; Yoon, Chi-Weon; Woo, Ramchan; Park, Se-Jeong; Yoo, Hoi‐Jun

doi:10.1109/mcom.2005.1561925

Cited by 21 publications

(1 citation statement)

References 5 publications

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“…The peak graphics performance is 50Mvertiecs/s for parallel projection at 200MHz operating frequency. The evaluation platform (Figure 8) was developed to evaluate and demonstrate mobile 3D graphics using a flexible topology and protocol [10]. It incorporates Intel's PXA255 host system since the prototype chip doesn't implement subsidiary hardware blocks such as memory management unit and an LCD controller.…”

Section: Evaluation Platformmentioning

confidence: 99%

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Sohn

Woo

Yoo

et al. 2006

Proceedings of the Design Automation &Amp;amp;amp; Test in Europe Conference

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Abstract:In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. The fixed-point co-processor architecture with dual operations realizes advanced 3-D graphics algorithms and various streaming multimedia functions in a single hardware while consuming low power. The instruction-wise clock gating on fixed-point SIMD datapath allows fine-grained power control in application-specific manner. The co-processor takes 10.2mm 2 in 0.18µm 6-metal standard CMOS logic process and achieves 50Mvertices/s graphics performance with 75.4mW power consumption. The implemented chip is successfully demonstrated on the development board equipped with software graphics library and evaluation environment.

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Section: Evaluation Platformmentioning

confidence: 99%

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Sohn

Woo

Yoo

et al. 2006

Proceedings of the Design Automation &Amp;amp;amp; Test in Europe Conference

View full text Add to dashboard Cite

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Mobile 3D Graphics SoC

Woo¹,

Sohn²,

Nam³

et al. 2010

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A 3D graphics pipeline has geometry operations for computing the attributes of vertices of polygons, and rendering operations for filling colors inside the polygons. The geometry stage generates vertex data from primitive input vertex attributes using transformation, lighting, and perspective projection. The rendering stage draws pixels from the vertex data computed in the geometry stage. First, vertex data are transformed into sets of 2D triangles using interpolation to calculate edge coordinates for each polygon. Then every pixel is rendered by shading and texture mapping. Alpha blending for translucent objects and depth comparison for hidden surface removal are performed during the rendering stage.The geometry operation is computation-intensive, and the rendering operation is data-intensive as well computation-intensive. To relieve bottlenecks, 3D graphics hardware has been evolving using fast, parallel datapaths such as multicore vector processors with 3D graphics-optimized memory systems [1,2].Mobile devices have limitations imposed by their power supply, their computational power, physical dimensions, and input devices. The fundamental problem is that mobile devices are powered by batteries.With regard to the hardware, the key issue to achieve good graphics performance and low power consumption is to reduce the internal data transactions between graphics-processing unit (GPU) and memory. Many researchers have focused on how to reduce or how to compress data transactions. As a result, various mobile graphics hardware approaches have been reported, including tile-based rendering [3], specialized embedded DRAM [4], and compression algorithms. They have employed various low-power techniques such as clock gating [5], power-down schemes, and voltage/ frequency scaling [5].With regard to the software, standard application programming interfaces (APIs) for embedded systems have been released: OpenGL-ES [6] and Microsoft Direct3D-Mobile [7]. The first is a subset of desktop OpenGL and adopts optimizations and Mobile 3D Graphics SoC: From Algorithm to Chip

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Application Platform

2010

Mobile 3D Graphics SoC

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Two steps are encountered in any design process: "planning" and "making." Certain procedures are followed when we want to perform meaningful tasks towards building a target structure. As the target structure takes on more complexity, well-established design procedures are essential. This applies in SoC design, which is strongly driven by its target applications such as multimedia and mobile communications. SoC engineers have to consider factors like quality, cost and delivery (QCD). In that sense, their design procedures naturally seek the reuse of previously developed techniques and materials at every possible design step.In a popular English dictionary, a "system" is defined as a set and a way of working in a fixed plan with networks of components. In addition to this, SoC requires one more idea, which is the integration of components on a single semiconductor chip. So it follows that we need to focus on two concepts: the fixed plan, and integration. We can catch the concept of predetermined architecture from the fixed plan; and integration involves the network and component-based design. Considering that modern digital gadgets require not only hardware (HW) components but also software (SW) programs, we can begin to see what the "platform" means in SoC design.The platform is a set of standalone modules that become the basis of the system. These standalone modules are pre-integrated and combine HW and SW componentswe call them the "reference architectures." They are also well-verified and have welldefined external interfaces. The platform guides what designers do, and this guidance determines the design flow. The platform concept helps us to design a more complicated and less buggy system within limited QCD factors by reusing and upgrading prebuilt HW and SW components.

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Low-power 3D graphics processors for mobile terminals

Cited by 21 publications

References 5 publications

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Mobile 3D Graphics SoC

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