Low-power 50% duty cycle corrector

Huang, Hong-Yi; Liang, Chia-Ming; Sun, Shi-Jia

doi:10.1109/iscas.2008.4541929

Cited by 12 publications

(5 citation statements)

References 14 publications

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“…7) is a balanced control stage [6]. The current-starving transistors MP0* and MN0* are used to adjust the sourcing current I up and the sinking current I dn , respectively.…”

Section: Control Stagementioning

confidence: 99%

“…The DCCs in existence can be generally categorized into Digital DCCs [1][2][3][4] and analog DCCs [5][6][7][8]. In general, digital DCCs are limited in the medium frequencies and of worse precision due to the unit delay cell.…”

Section: Introductionmentioning

confidence: 99%

“…In this structure we correct the duty cycle directly at the clock distribution path. The push-pull type control stage [6] is capable of adjusting the duty cycle for both directions. Besides, it is fast adjust and consumes less power.…”

Section: Introductionmentioning

confidence: 99%

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1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector

2011

Analog Integr Circ Sig Process

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A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 lm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz-3.5 GHz, and the duty cycle range of the input signal is from 0.1-99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz.

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“…7) is a balanced control stage [6]. The current-starving transistors MP0* and MN0* are used to adjust the sourcing current I up and the sinking current I dn , respectively.…”

Section: Control Stagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector

2011

Analog Integr Circ Sig Process

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“…The algorithm could automaticly adjust the provider node. The paper [5] proposed a least priority scheduling algorithm which at first obtained the smaller number data frames to ensure the start-up delay minimum. However, the algorithms didn't take into account how to calculate the data blocks priority according to itself factors including rarity, urgency and transmission time.…”

Section: Related Workmentioning

confidence: 99%

“…(3) If the client neighbor nodes number is less than or equal to a threshold value M , then turn to (4), otherwise turn to (5), remove these data blocks from Request-now ;…”

mentioning

confidence: 99%