Low Power 8T SRAM with High Stability and Bit Interleaving Capability

Lorenzo, Rohit; Pradeep, Dasari Lal; Kumar, Appikatla Phani

doi:10.1109/icefeet51821.2022.9848038

Cited by 7 publications

(1 citation statement)

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“…These SRAM cells all provide the highest level of stability. Single-ended SRAM architectures have been suggested in [22,23] in order to decrease power and area. These SRAM cells have bitline switching activity factors that are less than 0.5, which results in power savings.…”

Section: Earlier Reported Sram Cellsmentioning

confidence: 99%

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Kumar,

Lorenzo

2023

Eng. Res. Express

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Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18nm technology.

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Section: Earlier Reported Sram Cellsmentioning

confidence: 99%

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Kumar,

Lorenzo

2023

Eng. Res. Express

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A low power static noise margin enhanced reliable 8 T SRAM cell

Kumar,

Lorenzo

2024

Microsyst Technol

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9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage

Jiang,

Wen,

Meng

et al. 2024

Electronics Letters

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With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance.

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Low Power 8T SRAM with High Stability and Bit Interleaving Capability

Cited by 7 publications

References 0 publications

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

A low power static noise margin enhanced reliable 8 T SRAM cell

9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage

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