Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

Abstract

<p class="MsoNormal" style="text-align: left; margin: 0cm 0cm 0pt; layout-grid-mode: char;" align="left"><span class="text"><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;">In this paper a new low power and high performance adder cell using a new design style called “Bridge” is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply voltage variation from 0.65v to 1.5v with 0.05v steps.</span></span><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;"></span></p&gt

Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications

“…The main reason is that leakage current increases exponentially as the feature size shrinks. Based on the International Technology Roadmap for Semiconductors (ITRS), Kim et al report that subthreshold leakage power dissipation of a chip will exceed dynamic power dissipation at the 65nm feature size [1] [2]. Techniques for leakage power reduction can be grouped in two categories: state-preserving techniques where circuit state (present value) is retained and statedestructive techniques where the current boolean output value of the circuitmight be lost [1].…”

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

“…One of the important parameters in circuit design is the chip area. Therefore, the bridge structure might increase density or reduce the area of transistors in unit of area [29]. For instance, implementation of the majority function using bridge structure is illustrated in Fig.3.…”

“…In fact, structure of the bridge by shortening the route and reducing the transistors, reduces the complex and increases the efficiency of proposed 4-to-2 compressor cell [29][30][31]. Fig.4 shows a full adder cell designed using bridge structure.…”

Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool

“…Keivan Navi and Omid Kavehei [3] in February 2008 presented new low power and high performance adder cell using a new design style called using Bridge design style of the MOS transistor. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using named bridge transistors.…”