Low-power and high-speed SRAM cells for double-node-upset recovery

Cai, Shuo; Wen, Yan; Xie, Caicai; Wang, Weizheng; Yu, Fei

doi:10.1016/j.vlsi.2023.02.010

Cited by 5 publications

(1 citation statement)

References 32 publications

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“…(vi) (vii) [53] designed two radiation resistant SRAM cells named as LPDNUR and HSD-NUR that consists of four storage nodes and uses a two-input C-element structure that helps not only to provide recovery from the radiation effects but also, the technique is useful in reducing the average power consumption due to its stacking effect. Hence, both the designs consume lower leakage power in steady state.…”

Section: Rhwc12t Design (Year: July 2023)mentioning

confidence: 99%

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

Sengupta,

Yadav

2024

Preprint

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In memory, single event upset (SEU) and single event multiple node upset (SEMNU) have become the principal problems during the past four decades. Significant dependability issues arise from these upsets in a variety of applications such as space, terrestrial, military, and healthcare sector. The use of scaled on-chip memory devices to store private and sensitive data has grown dramatically in the last several years across all the sectors. Memory devices are seriously at risk from non-invasive side-channel assaults (SCAs), which extract secret and sensitive information as well as during SEU/SEMNU, which may flip stored secret and sensitive information. This article presents the history behind the emergence of radiation-hardened circuits and survey of several techniques to mitigate the impact of radiation over the past few decades along with SCA based on leakage power analysis. By educating the researchers on two crucial on-chip memory issues—radiation effect SEU/SEMNU and SCA—this work seeks to accelerate co-design efforts.

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Section: Rhwc12t Design (Year: July 2023)mentioning

confidence: 99%