2011
DOI: 10.1109/tcpmt.2010.2099590
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Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

Abstract: Abstract-This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV RC parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wirelength, clock power, slew, and skew in 3D clock network design. Secon… Show more

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Cited by 73 publications
(71 citation statements)
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“…Such high quality clock trees fully utilizing 3D design space can span entire dies as shown in Fig. 1 [7][8][9][10][11][12][13][14]. To safely apply highly optimized 3D clock trees distributed on multiple dies to a main production process of 3D ICs, we need to consider a new 3D process variation issue which is a special item distinguished from the conventional process variation for 2D clock trees.…”
Section: D Clock Tree and On-package Variationmentioning
confidence: 99%
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“…Such high quality clock trees fully utilizing 3D design space can span entire dies as shown in Fig. 1 [7][8][9][10][11][12][13][14]. To safely apply highly optimized 3D clock trees distributed on multiple dies to a main production process of 3D ICs, we need to consider a new 3D process variation issue which is a special item distinguished from the conventional process variation for 2D clock trees.…”
Section: D Clock Tree and On-package Variationmentioning
confidence: 99%
“…For the buffered clock tree designs, 3D clock tree synthesis (CTS) algorithms are studied in the works [7][8][9][10]. Minz, Zhao, and Lim [7] minimize and balance temperature dependent skew by relocating merging points of an initial zero skew clock tree.…”
Section: Introductionmentioning
confidence: 99%
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“…These networks are characterized by large capacitive loads and high-frequency switching. This requires a large amount of power, possibly up to 50% of total power consumption [34].…”
Section: Power/ground and Clock Networkmentioning
confidence: 99%
“…Our optimization methodology MoDo is presented in Section III; an experimental investigation is provided in Section IV. Our conclusions on optimizing deadspace for 3D ICs and its benefits are given in Section V. [25]) [19], [20] rarely aligned nonuniform; Thermal ≈ 2 − 40µm may be encouraged low -medium irregular small -medium contigous regions; [7] [8], [9], [27] possibly aligned nonuniform; Power/Ground ≈ 10 − 40µm strongly preferred low irregular small contigous regions; [7], [13], [14], [16] [11], [13], [14], [16] necessarily aligned nonuniform; Clock ≈ 2 − 20µm may be encouraged low irregular small contigous regions; [33] [33], [34] possibly aligned…”
Section: Introductionmentioning
confidence: 99%