Low?Power Architectures for Spike Sorting

Abstract

Abstract-Front-end integrated circuits for spike sorting will be useful in neuronal recording systems that engage a large number of electrodes. Detecting, sorting and encoding spike data at the front-end will reduce the data bandwidth and enable wireless communication. Without such data reduction, large data volumes need to be transferred to a host computer and typically heavy cables are required which constrain the patient or test animal. Front-end processing circuits must dissipate only a limited amount of power, due to supply constraints and heat restrictions. Two reduced complexity spike sorting algorithms are introduced, one based on Integral Transform and another on segmented PCA. The former achieves 98% of the precision of a PCA sorter, while requiring only 2.5% of the computational complexity. The latter algorithm is somewhat more accurate but incurs a higher complexity.

Hierarchical Adaptive Means (HAM) clustering for hardware-efficient, unsupervised and real-time spike sorting

“…These reduction methods can simply be in the form of data compression but several works have demonstrated hardware implementable feature extraction methods. These includes those based on derivative (Gibson et al, 2008;Paraskevopoulou et al, 2013), templates (Rizk et al, 2009), zero crossings (Kamboh and Mason, 2012) and neuronal spike shape and area (Zviagintsev et al, 2005), to name a few.…”

A sub-1µW neural spike-peak detection and spike-count rate encoding circuit

“…An obvious spike feature suitable as the alignment marker is its maximum. However, the maximum can be dislocated because of insufficient sampling, hence more elaborate alignment algorithms have been proposed [4]. By implementing the peak detection in the analogue domain, this issue can be eliminated.…”

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters

“…However, most algorithms for the two methods are computationally intensive and require tremendous hardware resources if implemented on chip. In order to facilitate on-chip implementations, several computationally economic approaches have been proposed, such as discrete derivatives [28], integral transform [29], and zero-cross features [30]. However, the effectiveness of these hardwarefriendly algorithms remains to be validated through realdata experiments.…”