Low power BIST based multiplier design and simulation using FPGA

Mishra, Bharti; Jain, Rita; Saraswat, Richa

doi:10.1109/sceecs.2016.7509284

Cited by 9 publications

(3 citation statements)

References 3 publications

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“…Advancements in LP-LFSR applications and test pattern generation are showcased to reduce power consumption while maintaining or improving fault detection efficiency. This highlights the growing need for power-efficient testing methods in VLSI circuit design [21][22][23].…”

Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

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This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

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Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

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“…With the characteristic of rapid hardware diagnosis, build-in self-test (BIST) was gradually used to test single lines [7]. It implemented the TPG and the ORA by configurable logic block (CLB) resources, thus greatly reducing the consumption of I/O resources [8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

et al. 2020

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With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

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“…Other factors such as low power consumption, performance, and the silicon area consumption of a random test pattern generator are also important. An LFSR is used to generate pseudo-random test patterns since it has excellent properties, such as a lower silicon area overhead in the chip [2]. In general, an LFSR consists of a series of flip-flops to perform the shift register function.…”

mentioning

confidence: 99%

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

Shivakumar

Senthilpari

Yusoff

2021

IJIE

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A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.

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Low power BIST based multiplier design and simulation using FPGA

Cited by 9 publications

References 3 publications

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

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