Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Abstract

Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

“…The CSLA structure in [28] was enhanced to use adaptive clock stretching operation where the enhanced structure was called cascade CSLA (C 2 SLA). Compared with the common CSLA structure, C 2 SLA uses more and different sizes of RCA blocks.…”

“…Hence, in this structure, the slack between the longest off-critical paths and the longest critical paths determines the maximum amount of the supply voltage scaling. Therefore, in the variable latency adders, for determining the critical paths activation, a predictor block, which works based on the inputs pattern, is required [28].…”

Low-power implementation of a 4×4 two-dimensional discrete Pascal Transform

“…In our work, we use an adaptive dual-supply voltage technique proposed in [6]. Traditionally the use of dual-supply voltage for the reduction of power consumption has relied on finding the non-critical part of the circuit and forcing that non-critical block to use the low supply voltage while keeping the timing critical blocks running at a high voltage.…”

“…Traditionally the use of dual-supply voltage for the reduction of power consumption has relied on finding the non-critical part of the circuit and forcing that non-critical block to use the low supply voltage while keeping the timing critical blocks running at a high voltage. The authors of [6] showed that the supply voltage to different parts of the adder block could be changed at runtime depending on the input pattern applied to the adder. The carry propagation in an adder is determined by the propagate signal P[k] which is given by the XOR of the inputs A[k] and B[k] being added.…”

Impact of Parameter Variations on Circuits and Microarchitecture

“…Suzuki, Jeong, and Roy use input variability to save power in a carry-select adder by exploiting delay differences according to input patterns. 20 Depending on the carry propagation length, this technique lowers supply voltage appropriately to finish the addition in the worst-case delay. Abdollahi, Fallah, and Pedram propose an approach that leverages the strong correlation between gate leakage current and input combinations by using the standby signal to shift in an input combination that minimizes leakage.…”