Low-power CMOS at Vdd=4kT/q

Bryant, A.; Brown, Jeffrey S.; Cottrell, P.E.; Ketchen, M. B.; Ellis-Monaghan, John; Nowak, E.

doi:10.1109/drc.2001.937856

Cited by 66 publications

(31 citation statements)

References 3 publications

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“…The current used to discharge the output of an inverter is the average of I NMOS with V GS =V DD as V DS drops from V DD to V DD /2. Using the transregional model numerically with |V GS |=V DD for each current calculation and with |V DS | shown gives: (12) Determining the parameters C eff , W eff , and L DP and using (11) for current in the equation for E L provides a numerical model for total energy for arbitrary gates. This model permits analysis across the full range of V DD .…”

Section: Numerical Modelmentioning

confidence: 99%

“…Emerging ultra-low power applications such as distributed sensor networks are a natural fit with subthreshold circuits. Special circuit techniques for improving robustness in deep subthreshold have been explored [12] [13]. Examining the energy-delay contours over V DD and V T shows that minimum energy operation occurs in the subthreshold operation regime for low-to-medium performance systems, and the optimum point changes depending on activity factor and threshold variation [2].…”

Section: Introductionmentioning

confidence: 99%

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Characterizing and modeling minimum energy operation for subthreshold circuits

Calhoun

Chandrakasan

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

154

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Subthreshold operation is emerging as an energy-saving approach to many new applications. This paper examines energy minimization for circuits operating in the subthreshold region. We show the dependence of the optimum V DD for a given technology on design characteristics and operating conditions. Solving equations for total energy provides an analytical solution for the optimum V DD and V T to minimize energy for a given frequency in subthreshold operation. SPICE simulations of a 200K transistor FIR filter confirm the analytical solution and the dependence of the minimum energy operating point on important parameters.

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Section: Numerical Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Characterizing and modeling minimum energy operation for subthreshold circuits

Calhoun

Chandrakasan

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

154

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show abstract

“…This configurable balancer is an extension of our previous work [20]. Our balancer is also different from the regulator presented in [21] since it uses an imbalance detector which has a better sensitivity. Also, it uses an amplifier in the feedback loop to enhance the sensitivity, and, it is configurable to support wide tuning.…”

Section: A Configurablementioning

confidence: 99%

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage

Gyvez

Corporaal

et al. 2010

IEEE J. Solid-State Circuits

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“…Minimum operation occurs when the pMOS and nMOS devices have the same current (e.g., [16]). Previous efforts have explored well biasing to match the device currents for minimum voltage operation of ring oscillators [12]. Sizing can create the same symmetry in device current.…”

Section: Sizing and Minimum Operating Voltagementioning

confidence: 99%

“…Emerging ultralow-power applications such as distributed sensor networks are a natural fit with subthreshold circuits. Special circuit techniques for improving robustness in deep subthreshold have been explored [12], [13]. Examining the energy-delay contours for digital circuits over and shows that minimum energy operation occurs in the subthreshold operation regime for low-to-medium performance systems, and the optimum point changes depending on activity factor and threshold variation [2].…”

Section: Introductionmentioning

confidence: 99%

Device sizing for minimum energy operation in subthreshold circuits

Calhoun

Wang

Chandrakasan

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

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Abstract-This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum DD and T to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum DD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-m test chip is used to compare normal sizing and sizing to minimize operational DD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.Index Terms-Energy model, low voltage operation, minimum energy point, subthreshold logic.

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Low-power CMOS at Vdd=4kT/q

Cited by 66 publications

References 3 publications

Characterizing and modeling minimum energy operation for subthreshold circuits

Characterizing and modeling minimum energy operation for subthreshold circuits

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage

Device sizing for minimum energy operation in subthreshold circuits

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