Characterizing and modeling minimum energy operation for subthreshold circuits

Calhoun, Benton H.; Chandrakasan, Anantha P.

doi:10.1145/1013235.1013265

Cited by 154 publications

(62 citation statements)

References 15 publications

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“…As the most frequently used network in the flip chip, the power consumption of the clock network has been increased to 40% [2]. Due to its low power consumption, clock tree is widely used in low power design.…”

Section: Clock Tree Under Low Voltagementioning

confidence: 99%

Clock Tree Synthesis and Optimization of SoCs under Low Voltage

He¹,

Huang²,

Wu³

et al. 2017

Proceedings of the 3rd Workshop on Advanced Research and Technology in Industry (WARTIA 2017)

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With the development of integrated circuits, the power consumption becomes a key problem in the design of integrated circuits. Reducing the operating voltage is an effective way to reduce power consumption. But the chip working voltage is reduced, brings more challenges to the chip design, which is mainly composed of process, voltage and temperature (PVT) variation instability on the performance of chips. According to the problem of clock tree network structure under low voltage, this paper puts forward a method of resistance process, voltage and temperature (PVT) variation clock tree design under low voltage, enhancing the stability of the chip, and ensuring the effectiveness of low voltage design.

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Section: Clock Tree Under Low Voltagementioning

confidence: 99%

Clock Tree Synthesis and Optimization of SoCs under Low Voltage

He¹,

Huang²,

Wu³

et al. 2017

Proceedings of the 3rd Workshop on Advanced Research and Technology in Industry (WARTIA 2017)

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“…Even though low power is the main focus, it is still innate for the designer to optimize secondary parameters such as robustness and performance. As a result of these efforts, works have been presented to optimize energy and delay, while performing computations with minimal error [1]- [3]. Additionally, efforts have been made to optimize devices such that circuits can be operated at medium frequencies in the order of tens to hundreds of megahertz [4].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems

Tolbert

Zhao

Lim

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits.Index Terms-Design automation, reliability, system analysis and design.

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“…Specifically, lowering supply voltage (V DD ) of the devices results in smaller energy per operation at the expense of slower performance. It has been shown that for most digital circuits, the minimum energy point lies in the subthreshold region (V DD < V T ) where devices are operated at weak inversion [3]. However, the performance of the circuits in the sub-threshold region is on the orders of kHz which might not be suitable for various energy constrained applications.…”

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confidence: 99%