Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Abstract

Abstract-Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This paper covers the main building blocks of a system implementation including digital logic, embedded memories and analog-to-digital conversion and describes the challenges and solutions to designing these blocks for low-voltage operation.

A Fully Biodegradable Battery for Self‐Powered Transient Implants

“…Introducing alginate hydrogel electrolyte and polyanhydride/poly(lactide‐ co ‐glycolide) (PLGA) coating can significantly prolong the lifetime of the battery system to be ≈13 d. Energy provided by the single Mg–MoO 3 cell is sufficient to power a red LED, a calculator, and the amplifier of an electrocardiogram (ECG) signal detector. The voltage and power provided by the battery could satisfy most of the ultralow‐power implantable devices as well as maintain robust functions, as the required voltage and power are typically in the range of ≈0.5–1.6 V and ≈10–1000 µW, respectively, thanks to the advanced design techniques and technology developments of complementary metal–oxide–semiconductor (CMOS) devices. The battery is fully degradable both in vitro and in vivo, and desirable biocompatibility of degradation products has been observed.…”

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

“…ltra-low power circuits are highly demanded in many green computing systems where ultralow voltage operation offers better energy efficiency with moderation in performance [1,2]. However, ultra-low voltage operation suffers from degraded noise margin and large performance variations due to aggressively scaled supply voltages [3].…”

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

“…Such supply voltage scaling is extremely beneficial to digital circuits and memory in mitigating the heating issues and increasing energy efficiency at the cost of slower speed. To overcome the reduced speed, parallelism is an effective method for digital circuits [2]. For analog circuits, there are many challenges in addition to the speed reduction such as the reduced signal-to-noise ratio (SNR), the smaller voltage headroom, and the increased effects of transistor variation at low voltages.…”