Low power CMOS dynamic latch comparators

Uthaichana, P.; Leelarasmee, Ekachai

doi:10.1109/tencon.2003.1273237

Cited by 29 publications

(6 citation statements)

References 4 publications

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“…Design has been simulated in both 180nm and 90nm process technologies and the results are compared with those in old paper [6]. Lower power consumption and high operational speed is most useful part of this design.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Here the main problem is more power consumption for the resistive dividing circuit in reset mode which causes power dissipation. [5], [6]. The circuit operation is given below and fig.1 shown for the resistive dividing Comparator.…”

Section: Resistive Dividing Comparatormentioning

confidence: 99%

“…At the end output with low conductance change to Vdd and high conductance is change to ground. [6], [7].…”

Section: Differential Current Sensing Comparatormentioning

confidence: 99%

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Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

Vishwakarma¹,

Sahu²,

Vishwakarma³

et al. 2013

IJCA

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In the present works, mainly power consumption of circuit is main issue for every designers. This paper mainly dealing with the implementation of CMOS Charge sharing latch Comparator and analysis of it using different parameter in 90nm.For the implementation of new design the features of two important Comparator are combined so that the power dissipation is reduced and speed of new design is increased. These two Comparator are Resistive Dividing Comparator and Differential Current sensing respectively. The simulation result is shown in 90nm technologies, for 2.4GHz clocked comparator by using 0.9V input. Again the result of 90nm technology is compared with 180nm technology to show the reduction of power and enhancement of speed. The implementation is done on the Cadence virtuoso design environment.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Resistive Dividing Comparatormentioning

confidence: 99%

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Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

Vishwakarma¹,

Sahu²,

Vishwakarma³

et al. 2013

IJCA

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“…Instead, a dynamic latch comparator is proposed, which consumes well below a milliwatt at low frequencies on the order of 10 MHz [6]. Dynamic latch comparators can have an offset voltage of hundreds of millivolts, so to keep the offset voltage low [7], a Lewis-Gray comparator is used [8]. This has a fair balance between complexity and power consumption.…”

Section: B Receivermentioning

confidence: 99%

Low-Power BPSK Inductive Data Link for an Implanted Intracortical Visual Prosthesis

Omisakin

Mestrom

Bentum

2019

2019 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

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“…Dynamic latch comparator can solve the power problem by removing the pre-amplifying stage [1], while achieving a smaller area. This paper focuses on charge sharing comparator as it combines the advantages of both, resistive dividing comparator & differential current sensing comparator.…”

Section: Introductionmentioning

confidence: 99%

Low Power CMOS Dynamic Latch Comparator using 0.18μm Technology

Singh¹,

Sharma²

2012

SMSJ

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The design and analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation.Simulation results are obtained in 0.18um with supply voltages of 1.8v respectively. The schematic of comparator is captured using Cadence Virtuoso schematic editor and simulated using the Cadence Spectre simulator.

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Low power CMOS dynamic latch comparators

Cited by 29 publications

References 4 publications

Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

Low-Power BPSK Inductive Data Link for an Implanted Intracortical Visual Prosthesis

Low Power CMOS Dynamic Latch Comparator using 0.18μm Technology

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