Low‐power column counter with a logical‐shift algorithm for CMOS image sensors

Park, K.; Kim, S.Y.

doi:10.1049/el.2019.2496

Cited by 6 publications

(4 citation statements)

References 5 publications

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“…The proposed CIS realizes low-power by using 1.5 V 4T-PPD while maintaining high image quality, which is suitable for IoT and AI applications. Parameter This work JSSC [6] TCASI [17] Sensor [18] JSSC [4] Process…”

Section: Discussionmentioning

confidence: 99%

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

Xu¹,

Chen²,

Kuang³

et al. 2022

J. Semicond.

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This paper presents a low-power high-quality CMOS image sensor (CIS) using 1.5 V 4T pinned photodiode (4T-PPD) and dual correlated double sampling (dual-CDS) column-parallel single-slope ADC. A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD. Dual-CDS is used to reduce random noise and the nonuniformity between columns. Dual-mode counting method is proposed to improve circuit robustness. A prototype sensor was fabricated using a 0.11 µm CMOS process. Measurement results show that the lag of the five-finger shaped pixel is reduced by 80% compared with the conventional rectangular pixel, the chip power consumption is only 36 mW, the dynamic range is 67.3 dB, the random noise is only 1.55 e– rms, and the figure-of-merit is only 1.98 e–·nJ, thus realizing low-power and high-quality imaging.

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Section: Discussionmentioning

confidence: 99%

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

Xu¹,

Chen²,

Kuang³

et al. 2022

J. Semicond.

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show abstract

“…To avoid this case, we designed an error-correction logic consisting of multiplexers (MUX) by adding an offset to the n + 1 column. For example, when the MSB of 3-bit SRAM (not used for edge detection) is 'H', the carry generation signal controls a mux to select the Qb instead of Q, leading to a '−1' code offset of the LSB of 5-bit static random access memory (SRAM) [28]. The edge-detector circuit can detect the positive and negative edges of D_out<n> and can detect the change in each bit output from the SRAM.…”

Section: Operation Principle Of the Edge-detection Cmos Image Sensormentioning

confidence: 99%

Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Jin¹,

Noh²,

Song³

et al. 2020

Sensors

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In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

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“…Since the algorithm allows the CNN to process large receptive fields with even fewer learnable weights, a CNN can operate much more efficiently than the typical artificial neural networks in processing high-dimensional data, such as images [17][18][19]. In that case, if the image resolution is 160 × 120, and 160 column-parallel high-bit (8-12 bits) ADCs are required, leading to 19,200 times the A/D conversion [20][21][22][23]. However, this is inefficient in terms of power consumption and chip area for the CIS.…”

Section: The Proposed Image Classification With the A-lwcnn Algorithmmentioning

confidence: 99%

Design of an Always-On Image Sensor Using an Analog Lightweight Convolutional Neural Network

Choi

Lee

Son

et al. 2020

Sensors

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This paper presents an always-on Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) using an analog convolutional neural network for image classification in mobile applications. To reduce the power consumption as well as the overall processing time, we propose analog convolution circuits for computing convolution, max-pooling, and correlated double sampling operations without operational transconductance amplifiers. In addition, we used the voltage-mode MAX circuit for max pooling in the analog domain. After the analog convolution processing, the image data were reduced by 99.58% and were converted to digital with a 4-bit single-slope analog-to-digital converter. After the conversion, images were classified by the fully connected processor, which is traditionally performed in the digital domain. The measurement results show that we achieved an 89.33% image classification accuracy. The prototype CIS was fabricated in a 0.11 μm 1-poly 4-metal CIS process with a standard 4T-active pixel sensor. The image resolution was 160 × 120, and the total power consumption of the proposed CIS was 1.12 mW with a 3.3 V supply voltage and a maximum frame rate of 120.

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Low‐power column counter with a logical‐shift algorithm for CMOS image sensors

Cited by 6 publications

References 5 publications

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Design of an Always-On Image Sensor Using an Analog Lightweight Convolutional Neural Network

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