Low‐power data encoding/decoding for energy‐efficient static random access memory design

Abstract

This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a '0' than a '1' benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

“…One of the most effective methods in evaluating the effectiveness of digital blocks is their application in real applications such as image processing [42,43]. With the increasing demand in this field, extensive studies have been done so far and image storage in bit-cells based on different methods such as approximate data storage structure [44,45], bit-data encoding/decoding algorithm [46] and lookup table (LUT) [47]. As a result of these algorithms, the process of store and read the data-bits of an image will be associated with a high probability of the distance between the results obtained in the simulation phase and the hardware implementation phase.…”

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

“…One of the most effective methods in evaluating the effectiveness of digital blocks is their application in real applications such as image processing [42,43]. With the increasing demand in this field, extensive studies have been done so far and image storage in bit-cells based on different methods such as approximate data storage structure [44,45], bit-data encoding/decoding algorithm [46] and lookup table (LUT) [47]. As a result of these algorithms, the process of store and read the data-bits of an image will be associated with a high probability of the distance between the results obtained in the simulation phase and the hardware implementation phase.…”

Design of SRAM Cell using Modified Lector and Dual Threshold Method Based on FINFET

“…However, many integrated devices require memory that is faster and more reliable. SRAM [1][2] contributes significantly to the low-power and highperformance capabilities that are necessary for VLSI applications. Due to process variances, SCEs, and leakage problems, rapid scale [3] has created reliability challenges.…”