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In this paper, we present a new 9T SRAM cell that has good write ability and improves read stability at the same time. Simulation results show that the proposed design increases read static noise margin and I ON /I OFF of read path by 219% and 113%, respectively, at supply voltage of 300-mV over conventional 6T SRAM cell in a 90-nm CMOS technology. The proposed design lets us reduce the minimum operating voltage of SRAM (VDD min ) to 350 mV, whereas conventional 6T SRAM cannot operate successfully with an acceptable failure rate at supply voltages below 725 mV. We also compared our design with three other SRAM cells from recent literature. To verify the proposed design, a 256-kb SRAM is designed using new 9T and conventional 6T SRAM cells. Operating at their minimum possible V DDs , the proposed design decreases write and read power per operation by 92% and 93%, respectively, over the conventional rival. The area of the proposed SRAM cell is increased by 83% over a conventional 6T one. However, due to large I ON /I OFF of read path for 9T cell, we are able to put 1k cells in each column of 256-kb SRAM block, resulting in the possibility for sharing write and read circuitries of each column between more cells compared with conventional 6T. Thus, the area overhead of 256-kb SRAM based on new 9T cell is reduced to 37% compared with 6T SRAM.

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In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors in each cell. This idea allows for bit-interleaving that makes the SRAM more reliable against the soft errors. One of the challenges of a conventional 6 transistor (6T) SRAM cell in sub-threshold region is sizing of its access transistors. Here by separating access transistors of reading and writing, we mitigate this challenge. By using a minimum-size access transistor for reading, probability of unsuccessful read reduces. To have a more successful write operation, we make one of the inverters of the cell that is fighting with the write access transistor, weaker during write operation by floating its supply voltage and ground rails. After write operation, this inverter returns back to normal mode. Simulation results in 90 nm CMOS technology show that our design satisfies 4.5-sigma criterion for reading and writing at supply voltage of 300 mV. Compared to conventional 6T SRAM cell, our design improves read-time and write-time significantly. For example at supply voltage of 500 mV, these improvements are 137 and 83 percents, respectively. Comparing power and energy consumption for single write operation of the proposed 7T SRAM cell at supply voltage of 300mV with conventional 6T SRAM cell at 800mV (i.e. minimum achievable voltage for this SRAM cell) shows improvements of 133.4X and 266.78X, respectively.