NISQ+: Boosting quantum computing power by approximating quantum error correction

Holmes, Adam; Jokar, Mohammad Reza Akbari; Pasandi, Ghasem; Ding, Yongshan; Pedram, Massoud; Chong, Frederic T.

doi:10.1109/isca45697.2020.00053

Cited by 59 publications

(59 citation statements)

References 55 publications

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“…Proof of this fact is that the decoder can achieve an 𝑓 max =125 MHz (clock period of 8 ns, with 78.7% of delay due to the routing and 21.3% due to the logic), which is equivalent to a total latency of 320 ns @ 𝐼𝑡 max =20. This latency is slightly smaller (80 ns less) than the time budget reported in [13], making this parallel architecture a promising candidate for real implementations of QLDPC codes for the QEC step, as with two cores of this architecture it can correct 𝑋 and 𝑍 errors for dual and non-dual containing codes, just changing the wiring between processing units in the last case. It is important to highlight that other serial implementations that process each CNU at the time, will allow higher convergence in the decoding but would increase the total latency 𝑀 times, not fulfilling the time constraints of the quantum system.…”

Section: Implementation Resultsmentioning

confidence: 96%

“…Although this range can be modified by the technology of the processor itself, the number of qubits and the encoding of the information, it allows hardware designers to have an order of magnitude to evaluate if the architectures are feasible to be applied in real systems or not. For example, taking as starting point the most restrictive time budget found in literature [14], [13] that is 400 ns, 2 the maximum frequency of the circuit needs to be 𝑓 max =2×20/400 ns=100 MHz, assuming 20 iterations. If both 𝐻 𝑋 and 𝐻 𝑍 are decoded with the same device, i.e.…”

Section: A Architecture For a Sb-ms Decodermentioning

confidence: 99%

“…This implies that the time to perform the error correction is bounded. Due to this, the implementation of any quantum error correction system has to consider the time budget of a single error correction round which is set between hundreds of nanoseconds [13] and several microseconds [14], to ensure that quantum information remains stable.…”

Section: Introductionmentioning

confidence: 99%

“…This time is reported as the period required to compute a syndrome generation cycle, and according to[13], a real hardware implementation of a decoder must be able to execute faster than syndrome data are generated as a prerequisite for tractable fault tolerant computation.…”

mentioning

confidence: 99%

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Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

Valls¹,

García-Herrero

Raveendran

et al. 2021

IEEE Access

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Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error correction codes and decoders has been established as a low-cost and feasible approach, with good results from a theoretical perspective, for mid and long-term architectures. While most of the authors are focused on the algorithms to improve the correction capability of quantum computers, without taking into account a fundamental implementation aspect for their deployment in a real system, i.e., their latency must be bounded to avoid the qubit decoherence, only a few propose hardware architectures and they just include time estimations of their decoding latency. However, a real implementation has not been shown yet. In this work, we analyze from the point of view of hardware implementation two algorithmic options based on quantum low-density parity-check (QLDPC) codes: a) belief propagation min-sum decoders combined with codes with good error-floor behavior and b) belief propagation min-sum decoders concatenated with ordered statistics decoders (OSDs) for codes with early error-floor. The bounds for the maximum clock frequency required by the decoders to decode within the qubit coherence time are established as a parameter to show if a practical implementation is possible with the present or near future FPGA technology. Furthermore, real implementation results for a Xilinx FPGA device are provided, showing that some solutions can meet the timing constraints set up by the state-of-the-art quantum processors.INDEX TERMS Quantum error correction, syndrome based decoding, ordered statistics, FPGA devices

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Section: Implementation Resultsmentioning

confidence: 96%

Section: A Architecture For a Sb-ms Decodermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

Valls¹,

García-Herrero

Raveendran

et al. 2021

IEEE Access

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“…In addition to the construction of QECCs with good parameters, practical QECCs need to equip with both efficient encoders and decoders. If the decoding is slower than the error accumulations, additional noise will be introduced during the syndrome decoding [18].…”

Section: Introductionmentioning

confidence: 99%

From Generalization of Bacon-Shor Codes to High Performance Quantum LDPC Codes

Fan¹,

Li²,

Wang³

et al. 2021

Preprint

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We utilize a concatenation scheme to construct new families of quantum error correction codes that include the Bacon-Shor codes. We show that our scheme can lead to asymptotically good quantum codes while Bacon-Shor codes cannot. Further, the concatenation scheme allows us to derive quantum LDPC codes of distance Ω(N2/3/loglogN) which can improve Hastings’s recent result [arXiv:2102.10030] by a polylogarithmic factor. Moreover, assisted by the Evra-Kaufman- Zémor distance balancing construction, our concatenation scheme can yield quantum LDPC codes with non-vanishing code rates and better minimum distance upper bound than the hypergraph product quantum LDPC codes. Finally, we derive a family of fast encodable and decodable quan- tum concatenated codes with parameters Q = [[N,Ω(√N),Ω(√N)]] and they also belong to the Bacon-Shor codes. We show that Q can be encoded very efficiently by circuits of size O(N) and depth O(√N), and can correct any adversarial error of weight up to half the minimum distance bound in O(√N) time. To the best of our knowledge, they are the most powerful quantum codes for correcting so many adversarial errors in sublinear time by far.

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