Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

Abstract

Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error correction codes and decoders has been established as a low-cost and feasible approach, with good results from a theoretical perspective, for mid and long-term architectures. While most of the authors are focused on the algorithms to improve the correction capability of quantum computers, without taking into account a fundamental implementation aspect for their deployment in a real system, i.e., their latency must be bounded to avoid the qubit decoherence, only a few propose hardware architectures and they just include time estimations of their decoding latency. However, a real implementation has not been shown yet. In this work, we analyze from the point of view of hardware implementation two algorithmic options based on quantum low-density parity-check (QLDPC) codes: a) belief propagation min-sum decoders combined with codes with good error-floor behavior and b) belief propagation min-sum decoders concatenated with ordered statistics decoders (OSDs) for codes with early error-floor. The bounds for the maximum clock frequency required by the decoders to decode within the qubit coherence time are established as a parameter to show if a practical implementation is possible with the present or near future FPGA technology. Furthermore, real implementation results for a Xilinx FPGA device are provided, showing that some solutions can meet the timing constraints set up by the state-of-the-art quantum processors.INDEX TERMS Quantum error correction, syndrome based decoding, ordered statistics, FPGA devices

Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures

“…To solve this issue, several options can be followed: the reduction of the number of iterations, the implementation in a more modern device, or the implementation over ASIC. The same happens with the largest code for the architecture described in [36].…”

“…In this section, we compare the full-parallel architecture for the 'Hard Syndrome' decoder from [36] to the 'Soft Syndrome' decoder introduced in this paper. The decoder was implemented for five different codes of different lengths and minimum distances ( 442, 68, 10 , 544, 80, 12 , 714, 100, 16 , 1020, 136, 20 , and 1428, 630, 24 ) in order to see the effect of scaling the number of qubits in hardware results.…”

“…The results are summarized in Tables 1 and 2. For the timing results, it can be seen that the decoders from [36] have an almost constant delay, except when the number of check nodes grows significantly ( 1428,630,24 ), in which case the delay increases due to the limitations of the internal routing of the FPGA device. Similar behavior can be observed for the 'Soft Syndrome' decoders, with the delay remaining almost constant for the three shorter codes and an increase of 2 ns for the denser code due to the routing.…”

“…Comparing the power consumption results, we can see that the 'Soft Syndrome' decoder consumes less power than the 'Hard Syndrome' decoder. This is due to the fact that the frequency of operation of our proposed decoder is smaller than the one that can be employed for the decoder from [36], reducing the overall power consumption. However, in all the cases the power consumption is beyond 1 W, which was reported as a possible power budget in [40] if the FPGA was set as close as possible to the quantum chip.…”

Branch-Assisted Sign-Flipping Belief Propagation Decoding for Topological Quantum Codes Based on Hypergraph Product Structure

“…A modified higher order OSD is proposed via a combination sweep method (OSD-CS) [25], and the authors also show that the quantum-version OSD can be used for topological codes. However, BP decoding concatenated with OSD will result in additional complexity and latency when compared to pure BP decoding, which is a disadvantage for practical applications [26].…”