An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs

Pasandi, Ghasem; Fakhraie, S.M.

doi:10.1109/ted.2014.2321295

Cited by 78 publications

(27 citation statements)

References 21 publications

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“…The simulations have been carried out using HSPICE with 16‐nm CMOS predictive technology model (PTM) 24 . Based on this technology model file, the threshold voltages ( V th ) for NMOS and PMOS are 0.47965 V and −0.43121 V, respectively, and nominal V DD is 0.7 V. To assess the relative performance of the proposed cell, its various design parameters have been compared with those of recently proposed SRAM cells such as read‐/write‐enhanced 8 T (WRE8T), 25 half‐select free bitline sharing 10T (HFBS10T), 19 differential writing 10T (10 T‐P1), 6 single‐ended 11T (SE11T), 17 and write‐assist low‐power 11T (WALP11T), 23 as shown in Figure 7. For meaningful comparisons, a 256 × 16 array has been considered to measure design metrics of the SRAM cells.…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

Improved read/write assist mechanism for 10‐transistor static random access memory cell

Abbasian

Gholipour

2022

Circuit Theory & Apps

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This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell.

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Section: Simulation Setup and Resultsmentioning

confidence: 99%

Improved read/write assist mechanism for 10‐transistor static random access memory cell

Abbasian

Gholipour

2022

Circuit Theory & Apps

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“…This cell also suffers from degraded HSNM of HS cells. Similar write-approach has also been followed in single ended cell proposed in [100] as shown in Fig. 28c.…”

Section: ) Ground Cut-off/floating or Virtual Ground Techniquementioning

confidence: 99%

“…28c. To alleviate the HS issue, the authors have employed a write-back technique with low area and power overheads [100]. The authors have modified this cell in [23] as shown in Fig.…”

Section: ) Ground Cut-off/floating or Virtual Ground Techniquementioning

confidence: 99%

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Ahmad¹,

Alam²,

Hasan³

et al. 2022

Preprint

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In order to meet the ultra-low power requirement of modern digital systems, voltage scaling is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled technologies significantly affect the stability of an Static Random Access Memory (SRAM) cell. This work provides an extensive review of various designs and techniques for solving issues related to SRAM cell stability. Decoupling the read operation is a commonly used technique for addressing read stability issue. Modified Schmitt-trigger based cell core, loop-cutting and additional discharge path based techniques have also been employed in the literature to enhance the read stability. However, the write-ability and stability of halfselected (HS) cells have been compromised in some of these technique. For write-ability enhancement, most of the techniques involve either weakening of pull-up/pull-down devices (to reduce the current responsible for storing the data) or strengthening of access transistors (to enhance the write current). It includes VDD/VSS -cut off or -floating, feedback cutting, multi-Vth write assist based cells. Apart from discussing the alternative bitcells, we also cover several peripheral read/write assist techniques. WL underdrive (WLUD) and dynamic WLUD are effective read assist techniques. WL -boost, WL -delayed boost, VDD-floating/lowering, transient VDD collapse, VSS raised, dual split control-VSS raised and negative BL (NBL) are among the peripheral techniques for enhancing write-ability. Furthermore, various techniques for mitigating the HS cell issues, such as write-back, column decoupled local wordline, modified bitinterleaving array architecture are discussed. Finally, the Cross-point selection based cell accessing in-built technique is illustrated. Through summary tables, conclusions are also derived for suggesting a circuit of choice for various categories.

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“…[13] precisely points to applications of IoT and make use of stack transistor technique for further curtailing leakage. A few other surveyed methodologies for development of SRAM topologies for sustaining stability with decline in power dissipation include sleep NMOS [14,15], read buffers [16,17] and controlling swing voltage [18,19]. Topologies utilizing singleended read or single-ended write methodologies are particularly employed for the purpose of curtailing switching and leakage power along with minimizing chip area.…”

Section: State Of the Artmentioning

confidence: 99%

“…In carrying out simulation of proposed SRAM cell and its comparative analysis in this work, we have utilized cadence virtuoso tool and Generic Process Design Kit 45-nm process technology model file [26,27]. Monte Carlo (MC) simulations with 4000 sample size have also been performed because the impact of process variations on the bit cell is also important to be analysed on certain parameters [14,28]. For investigating the impact of local variations, the variation in channel width (W), channel length (L), oxide thickness (t ox )and channel doping concentration [29] has been taken in to consideration.…”

Section: Simulation Set-upmentioning

confidence: 99%

Design of 10T SRAM cell with improved read performance and expanded write margin

Sachdeva

Tomar

2020

IET Circuits, Devices & Syst

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The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

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An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs

Cited by 78 publications

References 21 publications

Improved read/write assist mechanism for 10‐transistor static random access memory cell

Improved read/write assist mechanism for 10‐transistor static random access memory cell

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Design of 10T SRAM cell with improved read performance and expanded write margin

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