Low power DCT architecture for image compression

Vaithiyanathan, D.; Seshasayanan, R.

doi:10.1109/icaccs.2013.6938745

Cited by 9 publications

(7 citation statements)

References 14 publications

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“…Notice that the transformation proposed by the authors exhibits extremely high errors, which are emphasized in bold. We also report that the results linked to the transformations described in [14] and [15] display also acutely poor results as shown in Table 3.…”

Section: Irreproducibility Of Resultsmentioning

confidence: 87%

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Comments on ‘Area and power efficient DCT architecture for image compression’ by Dhandapani and Ramachandran

Cintra

Bayer

2017

EURASIP J. Adv. Signal Process.

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In [Dhandapani and Ramachandran, "Area and power efficient DCT architecture for image compression", EURASIP Journal on Advances in Signal Processing 2014, 2014:180] the authors claim to have introduced an approximation for the discrete cosine transform capable of outperforming several well-known approximations in literature in terms of additive complexity. We could not verify the above results and we offer corrections for their work.

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Section: Irreproducibility Of Resultsmentioning

confidence: 87%

“…In addition, we also considered the transformation in [14] and transformation in [15]. Results are shown in Table 1.…”

Section: Lack Of Energy Concentrationmentioning

confidence: 99%

Comments on ‘Area and power efficient DCT architecture for image compression’ by Dhandapani and Ramachandran

Cintra

Bayer

2017

EURASIP J. Adv. Signal Process.

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“…It can be obtained by using diagonal matrices with few non-zero coefficients. The elements of the low complexity diagonal matrix [12,13] are only powers of two, null multiplicative complexity is obtained. In Table 1, the computational complexity for various existing 8-point approximate DCTs are listed.…”

Section: Literature Reviewmentioning

confidence: 99%

Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

Thiruveni¹,

Shanthi²

2016

JSTS:Journal of Semiconductor Technology and Science

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“…In this paper, a low complexity multiplier-less DCT approximation is proposed, which is more essential for hardware realization. The derived fast algorithm requires only 12 additions, which is lesser than the number of additions required for any existing DCT approximation [17][18][19][20][21][22][23][24][25][26][27][29][30][31]. To examine the performance and trade-offs associated with the algorithm, we have coded the proposed as well as the existing algorithms [17,19,[21][22][23][24]26,27] in MATLAB and Verilog HDL, and it is synthesized with Xilinx Virtex 7 XC7V585T-2LFFG1761C device (Xilinx, Inc., San Jose, CA, USA) [36] and Cadence® RTL Compiler® [37] using UMC 90 nm standard cell library.…”

Section: Introductionmentioning

confidence: 99%

“…During the JPEG process, an image is divided into several 8 × 8 blocks and then the two-dimensional discrete cosine transform In general, the floating point DCT decorrelates the data being transformed so that most of its energy is packed in the low-frequency region, which is best suited for well-known image compression techniques [11][12][13][14][15] but does not meet the requirements of very fast real-time compression applications. For this reason, there has been huge interest in finding fixed point multiplication-free DCT algorithms [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] that can be implemented as low power and area efficient digital circuits, thus useful for mobile imaging devices.…”

Section: Introductionmentioning

confidence: 99%

Area and power efficient DCT architecture for image compression

Vaithiyanathan

Ramachandran

2014

EURASIP J. Adv. Signal Process.

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The discrete cosine transform (DCT) is one of the major components in image and video compression systems. The final output of these systems is interpreted by the human visual system (HVS), which is not perfect. The limited perception of human visualization allows the algorithm to be numerically approximate rather than exact. In this paper, we propose a new matrix for discrete cosine transform. The proposed 8 × 8 transformation matrix contains only zeros and ones which requires only adders, thus avoiding the need for multiplication and shift operations. The new class of transform requires only 12 additions, which highly reduces the computational complexity and achieves a performance in image compression that is comparable to that of the existing approximated DCT. Another important aspect of the proposed transform is that it provides an efficient area and power optimization while implementing in hardware. To ensure the versatility of the proposal and to further evaluate the performance and correctness of the structure in terms of speed, area, and power consumption, the model is implemented on Xilinx Virtex 7 field programmable gate array (FPGA) device and synthesized with Cadence® RTL Compiler® using UMC 90 nm standard cell library. The analysis obtained from the implementation indicates that the proposed structure is superior to the existing approximation techniques with a 30% reduction in power and 12% reduction in area.

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Low power DCT architecture for image compression

Cited by 9 publications

References 14 publications

Comments on ‘Area and power efficient DCT architecture for image compression’ by Dhandapani and Ramachandran

Comments on ‘Area and power efficient DCT architecture for image compression’ by Dhandapani and Ramachandran

Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

Area and power efficient DCT architecture for image compression

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