2016
DOI: 10.3390/jlpea6040020
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Low Power Design for Future Wearable and Implantable Devices

Abstract: With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter de… Show more

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Cited by 31 publications
(16 citation statements)
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“…From Equation (2), it can be concluded that the power consumption of the digital circuits can be reduced if the supply voltage, clock frequency and the capacitive load are kept at bare minimum. A deeper insight into the same is provided in [23,24,26]. For the SoC, a system clock of 6.78 MHz is used, generated by the internal clock regenerator circuit.…”
Section: Digital Power Consumptionmentioning
confidence: 99%
See 1 more Smart Citation
“…From Equation (2), it can be concluded that the power consumption of the digital circuits can be reduced if the supply voltage, clock frequency and the capacitive load are kept at bare minimum. A deeper insight into the same is provided in [23,24,26]. For the SoC, a system clock of 6.78 MHz is used, generated by the internal clock regenerator circuit.…”
Section: Digital Power Consumptionmentioning
confidence: 99%
“…The work presented in [25] yields a thorough insight of the main design tradeoffs in between the supply voltage, delay, robustness due to technology scaling and variability. Low power designs in the context of wearable and implantable devices are discussed in [26].…”
Section: Ultra Low Power Design Techniquesmentioning
confidence: 99%
“…The noise margins for two logic levels are expressed as: Relaying on fabrication processes advances of MOS transistors, it is possible that electrical and physical parameters which characterize MOS transistors can be controlled during fabrication process [1,3,6]. Therefore, we will examine the impact of these parameters on the particular magnitudes that characterize the CMOS inverter and based on them, can be defined the routes which lead to the design of the CMOS inverter with favorable performance according to the operation conditions and digital circuits based on CMOS logic [1,9,[15][16][17].…”
Section: The Role Of the Complementary Mosfet (Nmos And Pmos) Transismentioning
confidence: 99%
“…The PMU process the voltage delivered by the energy storage element (which can be a battery or supercapacitor) and delivers a regulated power supply to the rest of the system. It also provides of an interface circuit between the energy transducer and the storage element, and ensures that maximum transfer of power is achieved [13]. Figure 2 shows the general architecture of a PMU for EH purposes [14].…”
Section: Introductionmentioning
confidence: 99%