With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). dynamic power consumption, which means that a great deal of the power spent, is wasted solely on heat generation [1]. This can be dealt with by further researching cooling and packaging in order to avoid overheating the circuits; however, this is an expensive and time limited solution, so this paper addresses methods to generally reduce the overall power consumption of the systems.Since the Internet of Things (IoT) revolution, a new focus has been made on making smart phones, smart watches, tablets etc. even smaller whilst increasing the computation power. And with the recent interest in the Internet of Bio-Nano Things (IoBNT) [2], the focus has moved from just increasing the computation power to also creating extremely compact, ultra low power designs that enable small sensors and actuators to operate independently of wired data connections and external power sources. Especially for implanted sensors, the size restriction is crucial for the bio-compatibility and therefore, ...

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In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC.

Summary A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.