Equalization-Based Digital Background Calibration Technique for Pipelined ADCs

Abstract

In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC.

New digital background calibration method for pipelined ADCs

“…The calibration process begins from the third stage to the first stage recursively. A finite DC gain, capacitor mismatch and nonlinearity are set to 29 dB, 0.1% and −0.05, respectively, to realize MDAC imperfections (Zeinali et al , 2014). Consequently, α 1 and α 3 are set to 1.8 and −0.05, respectively.…”

“…Therefore, the input–output characteristic of residue amplifier is approximated by a third-order Taylor series polynomial, and neglecting higher-order terms as follows (Sahoo and Razavi, 2009; Panigada and Galton, 2009): where V res , V x and α 3 denote the output residue voltage, the input residue voltage and third-order nonlinearity of the residue amplifier, respectively. Furthermore, α 1 is defined as follows (Sahoo and Razavi, 2009; Montazerolghaem et al , 2015): where A represents finite DC gain and C s /C F is defined as follows: where δ represents the capacitor mismatch (Zeinali et al , 2014). Therefore, α 1 shows the capacitor mismatch together with finite DC gain of the residue amplifier.…”

Analog to Digital Converters (ADC): A Literature Review

“…presented a TI-ADC (timeinterleaved Analog to digital converter) achieving more bandwidth and highest sampling rate with a 5-bit resolution using a comparator of low power and latch along with track and hold amplifiers [19]. In this, the author has presented a 12-bit pipelined ADC and proposed a digital background calibration technology to improve its performance in cancelling the errors like capacitor mismatch, errors in gain and nonlinearities produced, on 90nm CMOS technology [20]. One more related article proposing SAR assisted digital slope ADC, had brought the leads of both SAR and digital slope ADCs in a hybrid ADC.…”

On Calibration Techniques for Pipelined ADCs

“…Here, the LMS algorithm has been used as the foreground technique to estimate the error coefficients which didn't need high accuracy signals for calibration. Here CNFA MDAC topology has been used to design the 1.5-bit/stage pipelined ADC [11]. The process of calibration works recessively in opposite direction by pipelined stages as shown in Figure 9.…”

“…ant for decidin nge the residu [8][9][10][11][12][13][14][15][16][17][18][19][20]. Because match.The effe Figure 3 of an ideal tr Since an op-a on-idealities o …”