Low-power design technique for decision-feedback equalisation in serial links

Abstract

A design technique for performing low-power decision-feedback equalisation for multi-Gbit/s serial links is presented. The technique systematically reduces the capacitive loading on the timing-critical node within the feedback loop of the equaliser. Based on the proposed technique, an architecture capable of both equalisation and digitisation of the received data is presented. Power efficiency of the proposed architecture is analysed and is compared with that of conventional analogue and loop-unrolled decision-feedback equalisers. The technique is validated through a proof-of-concept chip fabricated in 65 nm CMOS.Introduction: Decision-feedback equalisers (DFEs) it are a key component of high-data-rate, e.g. the emerging 40 to 100 Gbit/s, wireline receivers (RXs) [1]. In channels with a long impulse response tail, cancelling the post-cursor inter-symbol interference (ISI) using a DFE is a preferred choice over using a feed-forward equaliser (FFE). Such design choice is based on the fact that unlike FFEs, DFEs do not enhance the noise, or deliberately attenuate high-frequency components of the received signal [2]. However, DFEs suffer from a stringent requirement for timing closure within a 1 unit interval (UI) in the feedback loop. Depending on the speed and the required amount of post-cursor ISI cancellation, the power consumption of the DFE block may exceed the receiver's power budget [3]. Furthermore, given a CMOS technology, the implementation of high-speed DFEs may not be feasible due to capacitive self-loading of devices. In this Letter, we propose a DFE implementation technique that relaxes the trade-off among the power consumption, the data rate, and the amount of post-cursor ISI needed to be cancelled.

Hybrid optimisation method of sparse FIR DFEs based on reweighted ℓ 1 ‐norm minimisation and greedy algorithms

“…Therefore, the design of FIR equaliser with a small number of non‐zero taps (i.e. sparse FIR equaliser) is needed [1]. The designing of sparse FIR equalisers or filters in communication systems can be transformed into a sparse optimisation problem in the form of an ‐norm minimisation.…”

“…Initialise the zero taps position index set V (0) = ∅. Set the iteration number k = 1 and initialise the diagonal weighting matrix W (1) = diag(1, 1, . .…”

“…(2) To obtain the optimised non-zero taps values, solve the following constrained least-squares problem to minimise the excess mean square error of the sparse DFE L H f − d 2 2 as: 1) ,…”