Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Ahuja, Sumit; Lakshminarayana, Avinash; Shukla, Sandeep K.

doi:10.1007/978-1-4614-0872-7

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…Relevant Techniques Using low-power technologies Multiple threshold voltage [15], [49], [91], multiple supply voltage [12], [39], [47], [59], non-volatile memory [57] Scaling down the power for under-utilized resources Clock gating [1], [45], power gating [14], [16], [18], [31], behavioral observability don't care [22], [23], soft constraints [24], dynamic voltage and frequency scaling [46], [64], [82] Matching work to energy-efficient options Heterogeneous substrates [2], [3], [78], [87], [99], C-like parallel programming targeting FPGA [29], [72], [97] Cross-layer analysis Interconnect optimization [11], [13], [43], floorplanning optimization [38], [88], memory optimization [7], [21], [61], [95], high-level/logic synthesis [28] Trading-off other metrics for power Approximate hardware synthesis from behavioral description [67], error-constrained bit-width optimization [26], [63], [70] Spending power to save power Resource over-provisioning for hotspot reduction …”

Section: Optimization Categorymentioning

confidence: 99%

“…We can achieve significant saving in switching power of the register and the clock nets by inserting additional logic to disable the clock signals into these inactive registers. Ahuja et al [1] discuss methods of applying clock gating at various levels of granularities at the behavioral level and propose priority for clock gating decisions. Huang et al [45] address the area overhead of the clock gating logic and devise an optimization to minimize this overhead.…”

Section: Scaling Down the Power For Under-utilized Resourcesmentioning

confidence: 99%

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High-level Synthesis for Low-power Design

Zhang

Chen

Dai

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been increasingly difficult, if not already unsustainable. Complexity scaling dictates that this process must be automated with robust analysis and synthesis algorithms at a higher level of abstraction. Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. By allowing early access to the system architecture, high-level decisions during HLS can have a significant impact on the power and energy efficiency of the synthesized design. In this paper, we will discuss the recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations. We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. We will also describe the key power optimization challenges facing HLS today and outline potential opportunities in tackling these challenges.

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Section: Optimization Categorymentioning

confidence: 99%

Section: Scaling Down the Power For Under-utilized Resourcesmentioning

confidence: 99%

High-level Synthesis for Low-power Design

Zhang

Chen

Dai

et al. 2015

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

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“…This technique is called Power-Gating [16]. The same technique can also be applied on the clock instead of the power (i.e., clock gating [17]).…”

Section: Power Modeling Overview 31 Power Estimation and Power Reducmentioning

confidence: 99%

Multi-view Power Modeling Based on UML, MARTE and SysML

Gómez

Deantoni

Mallet

2012

2012 38th Euromicro Conference on Software Engineering and Advanced Applications

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The development of SoC involves different activities, usually driven by specialists. These specialists use specific languages and tools to manipulate their specific concepts. The problem is that the multiple views of the system are split into different tools with redundant information. It makes it difficult to ensure consistency as well as to change from one tool to another. We propose a multi-view model where each view represents the specialist concepts in a tool-agnostic manner. The model can be kept consistent by using explicit associations instead of redundancy and tool transformation can be performed to analysis-specific tools. The approach is based on uml and two of its extensions: marte and SysML. It is illustrated by adding specific views to specify power management techniques. The resulting model is then transformed into a tool-specific model; i.e., a model for Docea Aceplorer, a power analysis tool.

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“…High demand of portable devices such as laptops, mobile phones, personal digital assistance, smart cards, including Internet of Things (IoT), utilize intensively low-power design strategies and techniques such as clock gating, multi-supply multi voltage (MSMV), and power gating with state retention [1]. On the other hand, such low power strategies should not be adopted in real processor designs unless their correctness on the target processor has been fully verified.…”

Section: Introduction Imentioning

confidence: 99%

UPF-based formal verification of low power techniques in modern processors

Sharafinejad

Alizadeh

Fujita

2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Ensuring from the correctness of system on a chip (SoC) designs after the insertion of high level power management strategies that are disconnected from low level controlling signals, is a serious challenge to be addressed. This paper proposes a methodology for formally verifying dynamic power management strategies on implementations in modern processors. The proposed methodology is based on correspondence checking between a golden model without power features as a specification and a pipelined implementation with various power management strategies. Our main contributions in this paper are: 1) extracting Power Management Unit (PMU) from Unified Power Format (UPF) and Global Power Management (GPM), 2) automatically integrating PMU into the implementation and 3) checking the correspondence between two models with efficient symbolic simulation. The experimental results show that our method enables the designers to verify the designs with different power management strategies up to several thousands of lines of Register Transfer Level (RTL) code in minutes. In comparison with existing methods such as [7], our method reduces the number of state variables, the number of clauses, the number of symbolic simulation steps, and the CPU time by 11.04×, 17.57×, 2.08× and 13.71×, respectively. Keywords-Formal verification; global power management (GPM); unified power format (UPF); power management unit (PMU)

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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Cited by 7 publications

References 3 publications

High-level Synthesis for Low-power Design

High-level Synthesis for Low-power Design

Multi-view Power Modeling Based on UML, MARTE and SysML

UPF-based formal verification of low power techniques in modern processors

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