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Managing power consumption in a System -On-Chip (SoC) design is becoming increasingly important. SoCs generally consist of various co-processors. Accurate power estimation of these co-processors at the highest possible abstraction level helps in performing early power-aware design tradeoffs. This paper presents a methodology to create abstract statistical power models for hardware co-processors and its utilization at system-level for power estimation. In our systemlevel design environment co-processors are realized as Finite State Machine with Datapath (FSMD) and co-simulated with simulation model of ARM processor. Our power modeling methodology comprises of a learning and utilization phase. In the learning phase, we obtain state specific combinational signal toggling statistics from the FSMD simulation and derive a regression based power model. Consequently, we utilize this power model of FSMD in the full-chip simulation for faster computation of power estimates based on the activities of the FSMD model. Through a number of experimental designs, we show that with a relatively short learning phase no more than 6% worst-case and 4% rms error is observed with respect to the RTL power estimation techniques. I. INTRODUCTIONAccurate power estimation is one of the most important ingredients for any successful design methodology in embedded system or SoC design. Ability to estimate power accurately and early in the design flow helps in effectively controlling form factor, battery life and size, etc. Current power estimation techniques are well established at the RTL and lower levels of abstraction, while the techniques above RTL suffer from accuracy problems. One of the main reasons for such inaccuracy of power estimation at higher level is the lack of technology specific information and implementation details of the designs. It is very important to quantitatively reason the power consumption of a design at the early design stage.Current power estimation solutions comprise of spreadsheet, RTL simulation and power model based approaches. Spread-sheet based approach can be very useful in doing coarse-grain trade-offs. This approach is not very useful in obtaining application specific power numbers. On the other hand power estimation at the RTL requires design information in the form of Verilog/VHDL model, technology libraries, simulation

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