Low-Power Digital VLSI Design

Azizian

IEICE Electron. Express

et al. 2012

This paper is about the implementation of a novel booth encoder-decoder in a 0.35 µm CMOS technology. By introducing a new truth table, the gate level delay from inputs to partial products is reduced to two XOR logic gates plus one transistor which is the main advantage of the proposed architecture. Also, the gate count is reduced which reduces the power dissipation. In addition, because of similar paths from inputs to outputs, the latency for all paths becomes equal. Therefore, the output waveforms will be free of glitch. Post layout simulations demonstrate that the delay of the whole system is 350 ps.

Section: Initial Ideamentioning

confidence: 99%

Low latency, glitch-free booth encoder-decoder for high speed multipliers

Azizian

IEICE Electron. Express

et al. 2012

2009 IEEE/ACM International Symposium on Nanoscale Architectures

“…When compared to the Tagged Repair technique, this technique will require an extra (N + c sp ) single bit column tags (making it a total of 2×(N +c sp ) column tags). Considering a single bit SRAM cell requires 6 transistors [13], the overall CMOS area overhead in terms of transistor count can be calculated accordingly. The number of row tags will be equal to the Tagged Repair technique.…”

Section: B Modified Tagged Repair Techniquementioning

confidence: 99%

Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism

Srivastava

Melouki

Al-Hashimi

2009

Abstract-In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost. We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS'85 benchmark circuits synthesized into smaller sized LUTs.

Proceedings Tenth International Conference on VLSI Design

“…Let ip be the delay o f pth path arriving at input i. Then, the total width of hazard at the output of the gate is given by w = max p q ( ip ; jq ) f or all i j = 1 2 : : : k i 6 = j (1) The delay w is de ned as the di erential path delay for the gate. For a single input gate, like i n verter, w is 0 and the gate will never generate a hazard.…”

Section: Hazardsmentioning

confidence: 99%

“…One of these paths will have the delay that a rising transition takes to propagate, and the other path has the delay of the falling transition. Di erential path delay ( w) is computed for each gate according to Equation (1). All gates with single input will have w = 0.…”

Section: Increasing Delay For Hazard Filteringmentioning

confidence: 99%

See 1 more Smart Citation

Low-power design by hazard filtering

Agrawal

{ Before signals of a digital circuit reach steady state, gates can have multiple transitions. Since the power is dissipated in a CMOS circuit mainly due to transitions, the extra t r ansitions increase power consumption. These transitions are the hazard pulses generated by logic gates when signals arrive by paths of varying delays. The maximum width of a hazard pulse produced b y a gate is the maximum di erence b etween the delays of incident paths, which is generally much smaller than the clock period. We propose suppression of hazard pulses by increasing the delays of gates where hazards could have been generated. Thus, a hazard ltering gate has a delay which is at least as much as the di erential delay of its input paths. We give examples to illustrate the novel technique and also indicate that the overall reduction in the circuit speed may not be t o o much with proper sizing of transistors, while there c an be a signi cant reduction in power consumption.